Document
M74HC595
8-bit shift register with output latches (3-state)
SO16
TSSOP16
Features
• High speed: fMAX = 59 MHz (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.)
at TA= 25 °C • High noise immunity:
VNIH = VNIL = 28% VCC (min.) • Symmetrical output impedance:
– |IOH| = IOL = 6 mA (min.) for QA to QH – |IOH| = IOL = 4 mA (min.) for QH’ • Balanced propagation delays: tPLH ≅ tPHL • Wide operating voltage range: VCC (opr.) = 2 V to 6 V • Pin and function compatible with 74 series 595
• ESD performance – HBM: 2 kV – MM: 200 V – CDM: 1 kV
Datasheet - production data
Applications
• Automotive • Industrial • Computer • Consumer
Description
The M74HC595 device is a high speed CMOS 8-bit shift register with output latches (3-state) fabricated with silicon gate C2MOS technology.
This device contains an 8-bit serial in, parallel out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-state outputs. Separate clocks are provided for both the shift register and the storage register.
The shift register has direct overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
Table 1. Device summary
Order code
Temperature range
Package
Packing
Marking
M74HC595RM13TR M74HC595YRM13TR(1) M74HC595TTR M74HC595YTTR(1)
-55/+125 °C -40/+125 °C -55/+125 °C -40/+125 °C
SO16 SO16 (automotive grade)
TSSOP16 TSSOP16 (automotive grade)
Tape and reel
74HC595 74HC595Y
HC595 HC595Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent.
January 2014
This is information on a product in full production.
DocID1989 Rev 6
1/22
www.st.com
Contents
Contents
M74HC595
1
Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 SO16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 TSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M74HC595
1
Pin information
Pin information
4% 4& 4' 4( 4) 4* 4+ *1'
Pin no 1, 2, 3, 4, 5, 6, 7, 15
9 10 11 13 14 12 8 16
Figure 1. Pin connection and IEC logic symbols
9&& 4$ 6, * 5&. 6&. 6&/5 4+
* (1
! 5&. &
6&/5 5 65*
!
6&.
&
6, '
4$ 4% 4& 4' 4( 4) 4* 4+ 4+
$0
Table 2. Pin description
Symbol
Name and function
QA to QH QH’ SCLR SCK G SI RCK
Data outputs Serial data outputs Shift register clear input Shift register clock input Output enable input
Serial data input Storage register clock input
GND VCC
Ground (0 V) Positive supply voltage
$0
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Functional description
2
Functional description
M74HC595
Figure 2. Block diagram
6(5,$/,1
6&.
6&/5
67$*( 6+,)75(*,67(5
6(5,$/287
2+
5&.
%,7 6725$*(5(*,67(5
*
67$7( %8))(5
9&& *1'
4$ 4% 4& 4' 4( 4) 4* 4+
3$5$//(/2873876
1. This block diagram has not be used to estimate propagation delays.
Figure 3. Logic diagram
6&/5
6,
' 54 6&.
'5 4 6&.
'5 4 6&.
'5 4 6&.
'5 4 6&.
'5 4 6&.
6&.
5&.
'4 5&.
'4 5&.
'4 5&.
'4 5&.
'4 5&.
'5 4 6&.
'4 5&.
'5 4 6&.
'4 5&.
$0
4+
'4 5&.
*
4$
4%
4&
4'
4(
4)
4*
4+
1. This logic diagram has not be used to estimate propagation delays.
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$0
M74HC595
Functional description
SI
SCK
X
X
X
X
X
X
L
H
X
X
X
X
X
1. X: don’t care.
Inputs SCLR X X L H
H H X X
Table 3. Truth table(1)
RCK X X X X
X X
Outputs G
H
QA through QH outputs disable
L
QA through QH outputs enable
X
Shift register is cleared
X
First stage of S.R. becomes “L” other stages store the data of previous stage, respectively
X
First stage of S.R. becomes “H” other stages store the data of previous stage, respectively
X
State of S.R. is not changed
X
S.R. data is stored into storage .