Document
HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7130SA/LA IDT7140SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆ High-speed access – Commercial: 20/25/35/55/100ns (max.) – Industrial: 25/55/100ns (max.) – Military: 25/35/55/100ns (max.)
◆ Low-power operation – IDT7130/IDT7140SA — Active: 550mW (typ.) — Standby: 5mW (typ.) – IDT7130/IDT7140LA — Active: 550mW (typ.) — Standby: 1mW (typ.)
◆ MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140
◆ On-chip port arbitration logic (IDT7130 Only) ◆ BUSY output flag on IDT7130; BUSY input on IDT7140 ◆ INT flag for port-to-port communication ◆ Fully asynchronous operation from either port ◆ Battery backup operation–2V data retention (LA only) ◆ TTL-compatible, single 5V ±10% power supply ◆ Military product compliant to MIL-PRF-38535 QML ◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds ◆ Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP ◆ Green parts available, see ordering information
Functional Block Diagram
OEL CEL R/WL
OER CER R/WR
I/O0L- I/O7L
BUSYL(1,2) A9L A0L
I/O Control
I/O Control
Address Decoder
10
CEL OEL R/WL
MEMORY ARRAY
ARBITRATION and
INTERRUPT LOGIC
Address Decoder
10
CER OER R/WR
,
I/O0R-I/O7R
BUSYR(1,2) A9R A0R
INTL(2)
NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor.
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©2018 Integrated Device Technology, Inc.
INTR(2)
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IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry
Military, Industrial and Commercial Temperature Ranges
of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
A0 R A1 R A2 R A3 R A4 R A5 R A6 R A7 R A8 R A9 R I/O7R I/O6R
OER INTR BUSYR R/WR CER
VCC CEL R/WL BUSYL INTL OEL
A0L
42 41 40 39 38 37 36 35 34 33 32 31
43
30
44
29
45
28
46
27
47
26
48
7130/40
25
1
F48(4)
24
2
23
3
22
4
21
5
20
6
19
7 8 9 10 11 12 13 14 15 16 17 18
I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R GND I/O7L I/O6L I/O5L I/O4L I/O3L
INDEX
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A1 L A2 L A3 L A4 L A5 L A6 L A7 L A8 L A9 L I/O0L I/O1L I/O2L I/O2L I/O1L I/O0L A9 L A8 L A7 L A6 L A5 L A4 L A3 L A2 L A1 L
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. L48 package body is approximately .57 in x .57 in x .68 in.
F48 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram.
I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R
I/O4R I/O5R
18 17 16 15 14 13 12 11 10 9 8 7
19
6
20
5
21
4
22
3
23
2
24
7130/40
1
25
L48(4)
48
26
47
27
46
28
45
29
44
30
43
31 32 33 34 35 36 37 38 39 40 41 42
A0L OEL INTL BUSYL R/WL CEL
VCC CER R/WR BUSYR INTR OER
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I/O6R I/O7R
A9 R A8 R A7 R A6 R A5 R A4 R A3 R A2 R A1 R A0 R
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IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
CEL R/WL BUSYL INTL
OEL
A0L A1L A2L
A3L A4L A5L
A6L A7L A8L A9L
I/O0L I/O1L I/O2L I/O3L
I/O4L I/O5L I/O6L
I/O7L GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8 IDT7130/40 41
9 10
P or C P48(4,5)
&
40 39
11 C48(4,5) 38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VCC CER R/WR BUSYR INTR OER
A0R A1R
A2R A3R A4R A5R
A6R A7R A8R
A9R I/O7R I/O6R I/O5R
I/O4R I/O3R I/O2R
I/O1R I/O0R
,
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