AD5330 8-/10-/12-Bit DACs Datasheet

AD5330 Datasheet, PDF, Equivalent


Part Number

AD5330

Description

Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

Manufacture

Analog Devices

Total Page 28 Pages
Datasheet
Download AD5330 Datasheet


AD5330
2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
FEATURES
GENERAL DESCRIPTION
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel
interface. CS selects the device and data is loaded into the
input registers on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF or
0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
1 Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
VREF
3
VDD
12
POWER-ON
RESET
AD5330
BUF 1
GAIN 8
DB.. 7 20
DB0 13
CS 6
WR 7
CLR 9
LDAC 10
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
4 VOUT
RESET
POWER-DOWN
LOGIC
Figure 1. AD5330
11 5
PD GND
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.

AD5330
AD5330/AD5331/AD5340/AD5341
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 17
Digital-to-Analog Section ......................................................... 17
Resistor String ............................................................................. 17
DAC Reference Input................................................................. 17
Output Amplifier........................................................................ 17
Parallel Interface ............................................................................. 18
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 4.......................................................................... 16
Replaced Driving VDD from the Reference Voltage Section ..... 21
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
4/00—Revision 0: Initial Version
Double-Buffered Interface ........................................................ 18
Clear Input (CLR) ...................................................................... 18
Chip Select Input (CS)............................................................... 18
Write Input (WR) ....................................................................... 18
Load DAC Input (LDAC).......................................................... 18
High-Byte Enable Input (HBEN)............................................. 18
Power-On Reset.......................................................................... 18
Power-Down Mode ........................................................................ 19
Suggested Databus Formats .......................................................... 20
Applications Information .............................................................. 21
Typical Application Circuits ..................................................... 21
Driving VDD From the Reference Voltage ............................... 21
Bipolar Operation Using the AD5330/AD5331/
AD5340/AD5341......................................................................... 21
Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21
Programmable Current Source ................................................ 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
Rev. A | Page 2 of 28


Features 2.5 V to 5.5 V, 115 μA, Parallel Interf ace Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEAT URES GENERAL DESCRIPTION AD5330: sing le 8-bit DAC in 20-lead TSSOP AD5331: s ingle 10-bit DAC in 20-lead TSSOP AD534 0: single 12-bit DAC in 24-lead TSSOP A D5341: single 12-bit DAC in 20-lead TSS OP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V , 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Double-buffered input lo gic Guaranteed monotonic by design over all codes Buffered/unbuffered referenc e input options Output range: 0 V to VR EF or 0 V to 2 × VREF Power-on reset t o 0 V Simultaneous update of DAC output s via LDAC pin Asynchronous CLR facilit y Low power parallel data interface On- chip rail-to-rail output buffer amplifi ers Temperature range: −40°C to +105 °C APPLICATIONS Portable battery-power ed instruments Digital gain and offset adjustment Programmable voltage and cur rent sources Programmable attenuators Industrial process contro.
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