SNJ54HC590AFK

D 2-V to 6-V VCC Operation D High-Current 3-State Parallel Register Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns SN54HC590A . . . J OR W PACKAGE SN74HC590A . . . D, DW, OR N PACKAGE (TOP VIEW) QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 16 VCC 15 QA 14 OE 13 RCLK 12 CCKEN 11 CCLK 10 CCLR 9 RCO SN54HC590A, SN74HC590A 8ĆBIT BINARY COUNTERS WITH 3ĆSTATE OUTPUT REGISTERS SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D ±6-mA Output Drive at 5 V D Low Input Current of 1 µA Max D 8-Bit Counter With Register D Counter Has Direct Clear SN54HC590A . . . FK PACKAGE (TOP VIEW) QC QB NC VCC QA 3 2 1 20 19 QD 4 18 OE QE 5 17 RCLK NC 6 16 NC QF 7 15 CCKEN QG 8 14 CCLK 9 10 11 12 13 QH GND NC RCO CCLR description/ordering information NC − No internal connection The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CCLK) input of the following stage. CCLK and the register clock (RCLK) inputs are positive-edge t...