SNJ54HC42W

D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V SN54HC42 . . . J OR W PACKAGE SN74HC42 . . . D, N, OR NS PACKAGE (TOP VIEW) 01 12 23 34 45 56 67 GND 8 16 VCC 15 A 14 B 13 C 12 D 11 9 10 8 97 6 7 SN54HC42, SN74HC42 4ĆLINE TO 10ĆLINE DECODERS (1 of 10) SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Low Input Current of 1 µA Max D Full Decoding of Input Logic D All Outputs Are High for Invalid BCD Conditions D Also for Applications as 3-Line to 8-Line Decoders SN54HC42 . . . FK PACKAGE (TOP VIEW) VCC NC A 0 1 2 3 2 1 20 19 4 18 B 35 17 C NC 6 16 NC 47 15 D 58 14 9 9 10 11 12 13 8 NC GND NC − No internal connection description/ordering information These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic ensures that all inputs remain off for all invalid input conditions. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC42N SN74HC42N Tube of 40 SN74HC42D −40°C to 85°C SOIC − D Reel of 2500 Reel of 250 SN74HC42DR SN74HC42DT HC42 SOP − NS Reel of 2000 SN74HC42NSR HC42 CDIP − J Tube of 25 SNJ54HC42J SNJ54HC42J −55°C to 125°C CFP − W Tube of 150 SNJ54HC42W SNJ54HC42W LCCC − FK Tube of 55 SNJ54H...