PWM Switcher. TPS54310-EP Datasheet

TPS54310-EP Switcher. Datasheet pdf. Equivalent

TPS54310-EP Datasheet
Recommendation TPS54310-EP Datasheet
Part TPS54310-EP
Description Synchronous-Buck PWM Switcher
Feature TPS54310-EP; Typical Size (6,3 mm x 6,4 mm) TPS54310-EP www.ti.com .............................................
Manufacture etcTI
Datasheet
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Texas Instruments TPS54310-EP
Typical Size
(6,3 mm x 6,4 mm)
TPS54310-EP
www.ti.com ..................................................................................................................................................................................................... SLVS818 – APRIL 2008
3-V TO 6-V INPUT, 3-A OUTPUT, SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
1
2 Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
60-mMOSFET Switches for High Efficiency
at 3-A Continuous Output Source or Sink
Current
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Adjustable Output Voltage Down to 0.9 V With
1% Accuracy
Externally Compensated for Design Flexibility
Fast Transient Response
Wide PWM Frequency: Fixed 350 kHz, 550
kHz, or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
Low-Voltage High-Density Systems With
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for
High-Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
DESCRIPTION/ORDERING INFORMATION
As members of the SWIFT™ family of dc/dc regulators, the TPS54310 low input voltage high output current
synchronous buck PWM converter integrates all required active components. Included on the substrate with the
listed features are a true, high performance, voltage error amplifier that provides high performance under
transient conditions; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an
internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for
processor/logic reset, fault signaling, and supply sequencing.
The TPS54310 device is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in
quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated



Texas Instruments TPS54310-EP
TPS54310-EP
SLVS818 – APRIL 2008 ..................................................................................................................................................................................................... www.ti.com
Input
Simplified Schematic
VIN
PH
TPS54310
BOOT
PGND
VBIAS VSENSE
AGND COMP
Output
EFFICIENCY
vs
LOAD CURRENT
96
94
92
90
88
86
84
TA = 25°C
82 VI = 5 V
VO = 3.3 V
80
0 0.5
1
1.5 2 2.5
3
Load Current − A
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TJ
–55°C to 125°C
OUTPUT VOLTAGE
Adjustable Down to 0.9 V
PACKAGED DEVICES
PLASTIC HTSSOP (PWP)(2)(3)
TPS54310MPWPREP
TOPSIDE MARKING
54310EP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The PWP package is shipped taped and reeled with 2000 units per reel. See the application section of this data sheet for PowerPAD
drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VIN, SS/ENA, SYNC
VI Input voltage range
RT
VSENSE
BOOT
VO Output voltage range
VBIAS, PWRGD, COMP
PH
IO Output voltage range
PH
COMP, VBIAS
PH
Sink current
COMP
SS/ENA, PWRGD
Voltage differential
AGND to PGND
Continuous power dissipation
TJ Operating virtual-junction temperature range
Tstg Storage temperature
TPS54310
–0.3 to 7
–0.3 to 6
–0.3 to 4
–0.3 to 17
–0.3 to 7
–0.6 to 10
Internally Limited
6
6
6
10
±0.3
See Package Dissipation Rating
–55 to 150
–65 to 150
UNIT
V
V
V
V
V
V
mA
A
mA
mA
V
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54310-EP



Texas Instruments TPS54310-EP
TPS54310-EP
www.ti.com ..................................................................................................................................................................................................... SLVS818 – APRIL 2008
RECOMMENDED OPERATING CONDITIONS
VI
Input voltage
TJ
Operating virtual-junction temperature
MIN
MAX UNIT
3
6
V
–55
125
°C
PACKAGE DISSIPATION RATINGS(1) (2)
PACKAGE
20-Pin PWP with solder
20-Pin PWP without solder
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
26°C/W
57.5°C/W
TA = 25°C
POWER RATING
3.85 W(3)
1.73 W
TA = 70°C
POWER RATING
2.12 W
0.96 W
TA = 85°C
POWER RATING
1.54 W
0.69 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
a. 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch
b. 1.5 oz copper traces located on the top of the PCB
c. 1.5 oz copper ground plane on the bottom of the PCB
d. Ten thermal vias (see recommended land pattern in application section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
TJ = –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY VOLTAGE, VIN
VIN input voltage range
Quiescent current
fs = 350 kHz, SYNC = 0.8 V, RT open
fs = 550 kHz, SYNC 2.5 V, RT open, phase pin open
Shutdown, SS/ENA = 0 V
UNDERVOLTAGE LOCKOUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO(1)
BIAS VOLTAGE
Output voltage, VBIAS
VO
Output current, VBIAS(2)
I(VBIAS) = 0
CUMULATIVE REFERENCE
Vref Accuracy
REGULATION
Line regulation(1) (3)
Load regulation(1) (3)
IL = 1.5 A, fs = 350 kHz, TJ = 85°C
IL = 1.5 A, fs = 550 kHz, TJ = 85°C
IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C
IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10.
MIN
3
2.70
0.10
2.70
0.880
TYP
6.2
8.4
1
2.95
2.80
0.16
2.5
2.80
0.891
MAX UNIT
6V
9.6
12.8 mA
1.4
3
V
V
µs
2.95 V
100 µA
0.900 V
0.07
%/V
0.07
0.03
%/A
0.03
Copyright © 2008, Texas Instruments Incorporated
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