STEP-DOWN CONVERTER. TPS54318 Datasheet

TPS54318 CONVERTER. Datasheet pdf. Equivalent

TPS54318 Datasheet
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Part TPS54318
Description 3-A SYNCHRONOUS STEP-DOWN CONVERTER
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TPS54318
SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
TPS54318 2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
SWIFT™ Converter
1 Features
1 Two, 30-m(typical) MOSFETs for High-
Efficiency at 3-A loads
• Switching Frequency: 200 kHz to 2 MHz
• Voltage Reference Over Temperature: 0.8 V ± 1%
• Synchronizes to External Clock
• Adjustable Soft Start/Sequencing
• UV and OV Power-Good Output
• Low Operating and Shutdown Quiescent Current
• Safe Start-Up into Prebiased Output
• Cycle-by-Cycle Current Limit, Thermal and
Frequency Foldback Protection
• Operating Junction Temperature Range: –40°C to
150°C
• Thermally Enhanced 3 mm × 3 mm 16-pin WQFN
Package
• Create a Custom Design Using the TPS54318
With the WEBENCH® Power Designer
2 Applications
• Low-Voltage, High-Density Power Systems
• Point-of-Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
• Broadband, Networking and Optical
Communications Infrastructure
3 Description
TheTPS54318 device is a full-featured, 6-V, 3-A,
synchronous, step-down current-mode converter with
two integrated MOSFETs.
The TPS54318 device enables small designs by
integrating the MOSFETs, implementing current
mode control to reduce external component count,
reducing inductor size by enabling up to 2-MHz
switching frequency, and minimizing the device
footprint with a small, 3 mm x 3 mm, thermally
enhanced, QFN package.
The TPS54318 device provides accurate regulation
for a variety of loads with an accurate ±1% voltage
reference (VREF) over temperature.
Efficiency is maximized through the integrated 30-m
MOSFETs and a 350-μA typical supply current. Using
the EN pin, shutdown supply current is reduced to 2
μA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the soft-start pin.
An open-drain power-good signal indicates the output
is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protects
the device during an overcurrent condition.
For more SWIFT™ documentation, see the TI
website at www.ti.com/swift.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54318
WQFN (16)
3.00 mm × 3.00 mm
Simplified Schematic
VIN
TPS54318
VIN
BOOT
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Efficiency vs Output Current
100
95
EN
PH
VOUT
90
85
80
PWRGD
75
VSENSE
SS
RT/CLK
COMP
GND
AGND
PowerPad
70
65
60
55
50
0
0.5
1
1.5
2
Output Current (A)
VIN = 5 V
VOUT = 1.8 V
fSW = 1 MHz
2.5
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS54318
TPS54318
SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 17
8 Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1 Device Support .................................................... 32
11.2 Trademarks ........................................................... 32
11.3 Electrostatic Discharge Caution ............................ 32
11.4 Glossary ................................................................ 32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2014) to Revision C
Page
• update title ............................................................................................................................................................................. 1
Changes from Revision A (September 2013) to Revision B
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changes from Original (September 2009) to Revision A
Page
• Added "Instantaneous peak current" specification to the Current Limit section in the Electrical Characteristics table ........ 5
• Added Figure 22 to Typical Characteristics section ............................................................................................................... 9
2
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Copyright © 2009–2018, Texas Instruments Incorporated



Texas Instruments TPS54318
www.ti.com
5 Pin Configuration and Functions
RTE Package
16 Pin WQFN
(TOP VIEW)
TPS54318
SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
16 15 14 13
VIN 1
12 PH
VIN 2
GND 3
Thermal
Pad
GND 4
567
11 PH
10 PH
9 SS
8
PIN
NAME
NO.
AGND
5
BOOT
13
COMP
7
EN
15
3
GND
4
10
PH
11
12
PWRGD
14
RT/CLK
8
SS
9
1
VIN
2
16
VSENSE
6
Thermal Pad
Pin Functions
I/O (1)
DESCRIPTION
G Analog ground should be electrically connected to GND close to the device.
I
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
O
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
I
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to
set the on/off threshold (adjust UVLO) with two additional resistors.
G Power ground. This pin should be electrically connected directly to the power pad under the device.
O
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
over/under-voltage or EN shut down.
I/O Resistor Timing or External Clock input pin.
I/O Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft
I
Input supply voltage, 2.95 V to 6 V.
I
Inverting node of the transconductance (gm) error amplifier.
G
GND pin should be connected to the exposed power pad for proper operation. This power pad should
be connected to any internal PCB ground plane using multiple vias for good thermal performance.
(1) I = Input, O = Output, G = Ground
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS54318
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