Dual Positive-Edge-Triggered D-Type Flip-Flop
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
September 1986 Revis...
Description
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
September 1986 Revised July 2001
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM7474M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM7474N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR
CLR CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
(Note 1) (Note 1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
H = HIGH Logic Level X = Either LOW or HIGH Logic Level L ...
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