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Interconnect Switch. 89HPES32NT24BG2 Datasheet |
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32-Lane 24-Port PCIe® Gen2
System Interconnect Switch
®
89HPES32NT24BG2
Datasheet
Device Overview
The 89HPES32NT24BG2 is a member of the IDT family of PCI
Express® switching solutions. The PES32NT24BG2 is a 32-lane, 24-
port system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simulta-
neous peer-to-peer traffic flows. Target applications include multi-host or
intelligent I/O based systems where inter-domain communication is
required, such as servers, storage, communications, and embedded
systems.
Features
High Performance Non-Blocking Switch Architecture
– 32-lane, 24-port PCIe switch with flexible port configuration
– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
– Delivers up to 32 GBps (256 Gbps) of switching capacity
– Supports 128 Bytes to 2 KB maximum payload size
– Low latency cut-through architecture
– Supports one virtual channel and eight traffic classes
Port Configurability
– Four x8 stacks
• Two x8 stacks, each configurable as:
• One x8 port
• Two x4 ports
• Four x2 ports
• Eight x1 ports
• Several combinations of the above lane widths
• Two x8 stacks, each configurable as:
• One x8 port
• Two x4 ports
• Four x2 ports
• Several combinations of the above lane widths
– Automatic per port link width negotiation
(x8 x4 x2 x1)
– Crosslink support
– Automatic lane reversal
– Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
Innovative Switch Partitioning Feature
– Supports up to 8 fully independent switch partitions
– Logically independent switches in the same device
– Configurable downstream port device numbering
– Supports dynamic reconfiguration of switch partitions
• Dynamic port reconfiguration — downstream, upstream,
non-transparent bridge
• Dynamic migration of ports between partitions
• Movable upstream port within and between switch partitions
Non-Transparent Bridging (NTB) Support
– Supports up to 8 NT endpoints per switch, each endpoint can
communicate with other switch partitions or external PCIe
domains or CPUs
– 6 BARs per NT Endpoint
• Bar address translation
• All BARs support 32/64-bit base and limit address translation
• Two BARs (BAR2 and BAR4) support look-up table based
address translation
– 32 inbound and outbound doorbell registers
– 4 inbound and outbound message registers
– Supports up to 64 masters
– Unlimited number of outstanding transactions
Multicast
– Compliant with the PCI-SIG multicast
– Supports 64 multicast groups
– Supports multicast across non-transparent port
– Multicast overlay mechanism support
– ECRC regeneration support
Integrated Direct Memory Access (DMA) Controllers
– Supports up to 2 DMA upstream ports, each with 2 DMA chan-
nels
– Supports 32-bit and 64-bit memory-to-memory transfers
• Fly-by translation provides reduced latency and increased
performance over buffered approach
• Supports arbitrary source and destination address alignment
• Supports intra- as well as inter-partition data transfers using
the non-transparent endpoint
– Supports DMA transfers to multicast groups
– Linked list descriptor-based operation
– Flexible addressing modes
• Linear addressing
• Constant addressing
Quality of Service (QoS)
– Port arbitration
• Round robin
– Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
2013 Integrated Device Technology, Inc
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IDT 89HPES32NT24BG2 Datasheet
– High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
Clocking
– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible port clocking modes
• Common clock
• Non-common clock
• Local port clock with SSC (spread spectrum setting) and port
reference clock input
Hot-Plug and Hot Swap
– Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
– All ports support hot-plug using low-cost external I2C I/O
expanders
– Configurable presence-detect supports card and cable appli-
cations
– GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
– Hot-swap capable I/O
Power Management
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
– SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes associated with unused ports are turned off
• SerDes associated with unused lanes are placed in a low
power state
Reliability, Availability, and Serviceability (RAS)
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Initialization / Configuration
– Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
– Common switch configurations are supported with pin strap-
ping (no external components)
– Supports in-system Serial EEPROM initialization/program-
ming
On-Die Temperature Sensor
– Range of 0 to 127.5 degrees Celsius
– Three programmable temperature thresholds with over and
under temperature threshold alarms
– Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
– Ability to inject AER errors simplifies in system error handling
software validation
– On-chip link activity and status outputs available for several
ports
– Per port link activity and status outputs available using
external I2C I/O expander for all remaining ports
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Standards and Compatibility
– PCI Express Base Specification 2.1 compliant
– Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting
• Multicast
• VGA and ISA enable
• L0s and L1 ASPM
• ARI
Power Supplies
– Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES32NT24BG2 allows true multi-host or multi-
processor communications in a single device. Integrated DMA control-
lers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
A non-transparent bridge (NTB) is required when two PCI Express
domains need to communicate to each other. The main function of the
NTB block is to initialize and translate addresses and device IDs to
allow data exchange across PCI Express domains. The major function-
alities of the NTB block are summarized in Table 1.
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IDT 89HPES32NT24BG2 Datasheet
Block Diagram
x2
x4
x2
x8
x2
x4
x2
x8
x4
x2
x2
x4
x2
x2
x1
x1
x1
x1
x1
x1
x1
x1
S e rD e s S e rD es Se rD e s S e rD e s Se rD e s S erD es S e rD e s S e rD e s
D L /T L
D L /T L
D L/T L
D L /T L
D L/T L
D L /T L
D L/T L
D L /T L
NTB
NTB
NTB
N TB
DMA
24-Port Sw itch Core
DMA
NTB
NTB
NTB
NTB
D L /T L
D L /T L
D L /T L
D L /T L
D L /T L
D L /T L
D L /T L
D L /T L
S e rD e s Se rD e s S e rD es Se rD e s S e rD es Se rD e s S erD es S e rD e s
x1
x1
x1
x1
x1
x1
x1
x1
x2
x2
x4
x2
x2
x4
x8
Figure 1 PES32NT24BG2 Block Diagram
x2
x4
x2
x8
x2
x4
x2
Function
Number
Description
NTB ports
Mapping table
entries
Mapping windows
Address translation
Doorbell registers
Message registers
Up to 8
Up to 64 for entire
device
Six 32-bits or three
64-bits
Direct-address and
lookup table trans-
lations
32 bits
4 inbound and out-
bound registers of
32-bits
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets
a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Table 1 Non-Transparent Bridge Function Summary
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