OPERATIONAL AMPLIFIER. UPC4570G2 Datasheet

UPC4570G2 AMPLIFIER. Datasheet pdf. Equivalent

UPC4570G2 Datasheet
Recommendation UPC4570G2 Datasheet
Part UPC4570G2
Description DUAL OPERATIONAL AMPLIFIER
Feature UPC4570G2; DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC4570 ULTRA LOW-NOISE, WIDEBAND, DUAL OPERATIONAL AMP.
Manufacture NEC
Datasheet
Download UPC4570G2 Datasheet




NEC UPC4570G2
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4570
ULTRA LOW-NOISE, WIDEBAND, DUAL OPERATIONAL AMPLIFIER
DESCRIPTION
The µPC4570 is an ultra low-noise, wideband high slew-rate, dual operational amplifier. Input equivalent noise is three
times better than the conventional 4558 type op-amps. The gain bandwidth products and the slew-rate are seven times
better than 4558. In spite of fast AC performance, the µPC4570 is extremely stable under voltage-follower circuit
conditions. Supply current is also improved compared with conventional wideband op-amps. The µPC4570 is an
excellent choice for pre-amplifiers and active filters in audio, instrumentation, and communication circuits.
FEATURES
Ultra low noise : en = 4.5 nV/Hz
High slew rate : 7 V/µs
High gain bandwidth product : GBW = 15 MHz at 100 kHz
Internal frequency compensation
ORDERING INFORMATION
Part Number
Package
µPC4570C
8-pin plastic DIP (7.62 mm (300))
µPC4570G2
8-pin plastic SOP (5.72 mm (225))
µPC4570HA
9-pin plastic slim SIP
EQUIVALENT CIRCUIT (1/2 Circuit)
V+
R1
Q7
Q5
Q14
Q11
Q13
Q8
R7
Q16
II
Q1
Q2
Q9
IN
R5
R6
C2
R8
R9
Q12 Q15
Q6
Q3
Q4
Q10
OUT
R2
C1 R3
R4
R10
D
V
PIN CONFIGURATION (Top View)
µPC4570C, 4570G2
OUT1 1
1
–+
I I1 2
I N1 3
8 V+
7 OUT2
2
+–
6 I I2
V4
5 IN2
µPC4570HA
1
2
–+
+–
123456789
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G10528EJ6V0DS00 (6th edition)
(Previous No. IC-1996)
The mark 5 shows major revised points.
©
Date Published October 2001 NS CP(K)
Printed in Japan
1987



NEC UPC4570G2
µPC4570
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Symbol
Ratings
Unit
Voltage between V+ and VNote 1
V+ - V
–0.3 to +36
V
Differential Input Voltage
VID
Input Voltage Note 2
VI
Output Voltage Note 3
VO
Power Dissipation
C Package Note 4
PT
G2 Package Note 5
HA Package Note 4
Output Short Circuit Duration Note 6
±30
V
V–0.3 to V+ +0.3
V
V–0.3 to V+ +0.3
V
350
mW
440
mW
350
mW
10
sec
Operating Ambient Temperature
TA
–20 to +80
°C
Storage Temperature
Tstg
–55 to +125
°C
Notes 1. Reverse connection of supply voltage can cause destruction.
2. The input voltage should be allowed to input without damage or destruction. Even during the transition period
of supply voltage, power on/off etc., this specification should be kept. The normal operation will establish
when the both inputs are within the Common Mode Input Voltage Range of electrical characteristics.
3. This specification is the voltage which should be allowed to supply to the output terminal from external without
damage or destruction. Even during the transition period of supply voltage, power on/off etc., this specification
should be kept. The output voltage of normal operation will be the Output Voltage Swing of electrical
characteristics.
4. Thermal derating factor is –5.0 mW/°C when operating ambient temperature is higher than 55°C.
5. Thermal derating factor is –4.4 mW/°C when operating ambient temperature is higher than 25°C.
6. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4 and
Note 5.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Output Current
Source Resistance
Capacitive Load (AV = +1)
Symbol
MIN.
TYP.
MAX.
Unit
V±
±4
±16
V
IO
±10
mA
RS
50
k
CL
100
pF
2
Data Sheet G10528EJ6V0DS



NEC UPC4570G2
µPC4570
ELECTRICAL CHARACTERISTICS (TA = 25°C, V± = ±15 V)
Parameter
Symbol
Conditions
Input Offset Voltage
Input Offset Current Note
Input Bias Current Note
Large Signal Voltage Gain
Supply Current
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode Input Voltage Range
Slew Rate
Gain Bandwidth Product
Unity Gain Frequency
Phase Margin
Total Harmonic Distortion
Input Equivalent Noise Voltage
Input Equivalent Noise Voltage Density
Input Equivalent Noise Current Density
Channel Separation
VIO
IIO
IB
AV
ICC
CMR
SVR
Vom
VICM
SR
GBW
funity
φunity
THD
Vn
en
in
RS 50
RL 2 k, VO = ±10 V
IO = 0 A, Both Amplifiers
RL 10 k
RL 2 k
RL 2 k
fO = 100 kHz
open loop
open loop
VO = 3 Vr.m.s., f = 20 Hz to
20 kHz (Figure1)
RIAA (Figure2)
FLAT+JIS A, RS = 100
(Figure3)
fO = 10 Hz, RS = 100
fO = 1 kHz, RS = 100
fO = 1 kHz
f = 20 Hz to 20 kHz
MIN.
30,000
80
80
±12
±10
±12
5
10
TYP.
±0.3
±10
100
300,000
5
100
100
±13.4
±12.8
±14
7
15
7
50
0.002
MAX.
±5
±100
400
8
Unit
mV
nA
nA
mA
dB
dB
V
V
V
V/µs
MHz
MHz
degree
%
0.9
0.53
0.65
µVr.m.s.
µVr.m.s.
5.5
nV/Hz
4.5
nV/Hz
0.7
pA/Hz
120
dB
Note Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.
Data Sheet G10528EJ6V0DS
3







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