POSITIVE-AND GATE. SN74AC11-EP Datasheet

SN74AC11-EP GATE. Datasheet pdf. Equivalent

SN74AC11-EP Datasheet
Recommendation SN74AC11-EP Datasheet
Part SN74AC11-EP
Description TRIPLE 3-INPUT POSITIVE-AND GATE
Feature SN74AC11-EP; SN74AC11ĆEP TRIPLE 3ĆINPUT POSITIVEĆAND GATE D Controlled Baseline − One Assembly/Test Site, One Fa.
Manufacture etcTI
Datasheet
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etcTI SN74AC11-EP
SN74AC11ĆEP
TRIPLE 3ĆINPUT POSITIVEĆAND GATE
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SCLS557 − JANUARY 2004
D 2-V to 6-V VCC Operation
D Inputs Accept Voltages to 6 V
D Max tpd of 7.5 ns at 5 V
D OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 VCC
13 1C
12 1Y
11 3A
10 3B
9 3C
8 3Y
description/ordering information
The SN74AC11 device contains three independent 3-input AND gates. This device performs the Boolean
function Y = A B C or Y = A + B + C in positive logic.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tape and reel
Tape and reel
SN74AC11IDREP§
SN74AC11IPWREP
SAC11EP
SAC11EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
§ Product Preview
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
H
L
X
X
L
X
L
X
L
X
X
L
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
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etcTI SN74AC11-EP
SN74AC11ĆEP
TRIPLE 3ĆINPUT POSITIVEĆAND GATE
SCLS557 − JANUARY 2004
logic diagram, each gate (positive logic)
1A 1
1B 2
1C 13
2A 3
2B 4
2C 5
3A 11
3B 10
3C 9
12 1Y
6
2Y
8 3Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265



etcTI SN74AC11-EP
SN74AC11ĆEP
TRIPLE 3ĆINPUT POSITIVEĆAND GATE
SCLS557 − JANUARY 2004
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v Input transition rise or fall rate
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
2
6V
2.1
3.15
V
3.85
0.9
1.35 V
1.65
0 VCC V
0 VCC V
−12
−24 mA
−24
12
24 mA
24
8 ns/V
TA
Operating free-air temperature
−40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN TYP MAX
3V
2.9 2.99
IOH = −50 µA
4.5 V
5.5 V
4.4 4.49
5.4 5.49
VOH
IOH = −12 mA
IOH = −24 mA
IOH = −75 mA†
3V
4.5 V
5.5 V
5.5 V
3V
2.56
3.86
4.86
0.002 0.1
IOL = 50 µA
4.5 V
5.5 V
0.001 0.1
0.001 0.1
VOL
IOL = 12 mA
3V
0.36
4.5 V
0.36
IOL = 24 mA
5.5 V
0.36
IOL = 75 mA†
5.5 V
II
VI = VCC or GND
5.5 V
±0.1
ICC
VI = VCC or GND, IO = 0 5.5 V
2
Ci
VI = VCC or GND
5V
2.6
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
MIN MAX
2.9
4.4
5.4
2.46
3.76
4.76
3.85
0.1
0.1
0.1
0.44
0.44
0.44
1.65
±1
20
UNIT
V
V
µA
µA
pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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