Document
Data sheet acquired from Harris Semiconductor SCHS186E
September 1997 - Revised August 2003
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393
High-Speed CMOS Logic Dual 4-Stage Binary Counter
[ /Title (CD74 HC393 , CD74 HCT39 3) /Subject (High Speed CMOS
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative-Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC393 and ’HCT393 are 4-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.
Ordering Information
PART NUMBER CD54HC393F3A CD54HCT393F3A CD74HC393E CD74HC393M CD74HC393MT CD74HC393M96 CD74HCT393E CD74HCT393M CD74HCT393MT CD74HCT393M96
TEMP. RANGE (oC)
-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC393, CD54HCT393 (CERDIP)
CD74HC393, CD74HCT393 (PDIP, SOIC) TOP VIEW
1CP 1 1MR 2 1Q0 3 1Q1 4 1Q2 5 1Q3 6 GND 7
14 VCC 13 2CP 12 2MR 11 2Q0 10 2Q1 9 2Q2 8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 Functional Diagram
1 1CP
2 1MR
13 2CP
12 2MR
BINARY COUNTER
BINARY COUNTER
3 1Q0
4 1Q1
5 1Q2
6 1Q3
11 2Q0
10 2Q1
9 2Q2
8 2Q3
GND = 7 VCC = 14
TRUTH TABLE
OUTPUTS
CP COUNT
Q0
Q1
Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
CP COUNT
MR
OUTPUT
↑
L
No Change
↓
L
Count
X
H
LLLL
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 Logic Diagram
1(13) CP
2(12) MR
ΦQ
ΦQ R
ΦQ
ΦQ R
ΦQ
ΦQ R
ΦQ
ΦQ R
3(11) Q0
4(10) Q1
5(9) Q2
6(8) Q3
3
CD54HC393,.