CD74HCT393M

Data sheet acquired from Harris Semiconductor SCHS186E September 1997 - Revised August 2003 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 High-Speed CMOS Logic Dual 4-Stage Binary Counter [ /Title (CD74 HC393 , CD74 HCT39 3) /Subject (High Speed CMOS Features Description Fully Static Operation Buffered Inputs Common Reset Negative-Edge Clocking Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC393 and ’HCT393 are 4-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. Ordering Information PART NUMBER CD54HC393F3A CD54HCT393F3A CD74HC393E CD74HC393M CD74HC393MT CD74HC393M96 CD74HCT393E CD74HCT393M CD74HCT393MT CD74HCT393M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55...