Three-State Non-Inverting/Inverting. CD74HCT368E Datasheet

CD74HCT368E Non-Inverting/Inverting. Datasheet pdf. Equivalent

CD74HCT368E Datasheet
Recommendation CD74HCT368E Datasheet
Part CD74HCT368E
Description Three-State Non-Inverting/Inverting
Feature CD74HCT368E; CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Data sheet acquired from Harris Semiconductor.
Manufacture etcTI
Datasheet
Download CD74HCT368E Datasheet




Texas Instruments CD74HCT368E
CD54/74HC367, CD54/74HCT367,
CD54/74HC368, CD74HCT368
Data sheet acquired from Harris Semiconductor
SCHS181D
November 1997 - Revised October 2003
High-Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
[ /Title
(CD74
HC367
,
CD74
HCT36
7,
CD74
HC368
,
CD74
HCT36
8)
/Sub-
ject
(High
Speed
Features
Ordering Information
• Buffered Inputs
• High Current Bus Driver Outputs
• Two Independent Three-State Enable Controls
Typical Propagation Delay
CL = 15pF, TA = 25oC
tPLH,
tPHL
=
8ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC367F3A
-55 to 125
16 Ld CERDIP
CD54HC368F3A
-55 to 125
16 Ld CERDIP
CD54HCT367F3A
-55 to 125
16 Ld CERDIP
CD74HC367E
-55 to 125
16 Ld PDIP
CD74HC367M
-55 to 125
16 Ld SOIC
CD74HC367MT
-55 to 125
16 Ld SOIC
CD74HC367M96
-55 to 125
16 Ld SOIC
CD74HC368E
-55 to 125
16 Ld PDIP
CD74HC368M
-55 to 125
16 Ld SOIC
CD74HC368MT
-55 to 125
16 Ld SOIC
CD74HC368M96
-55 to 125
16 Ld SOIC
CD74HCT367E
-55 to 125
16 Ld PDIP
CD74HCT367M
-55 to 125
16 Ld SOIC
CD74HCT367MT
-55 to 125
16 Ld SOIC
CD74HCT367M96
-55 to 125
16 Ld SOIC
CD74HCT368E
-55 to 125
16 Ld PDIP
CD74HCT368M
-55 to 125
16 Ld SOIC
CD74HCT368MT
-55 to 125
16 Ld SOIC
CD74HCT368M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate
CMOS three-state buffers are general purpose high-speed
non-inverting and inverting buffers. They have high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits possess the low
power dissipation of CMOS circuitry, yet have speeds compara-
ble to low power Schottky TTL circuits. Both circuits are capable
of driving up to 15 low power Schottky inputs.
The ’HC367 and ’HCT367 are non-inverting buffers, whereas
the ’HC368 and CD74HCT368 are inverting buffers. These
devices have two output enables, one enable (OE1) controls 4
gates and the other (OE2) controls the remaining 2 gates.
The ’HCT367 and CD74HCT368 logic families are speed, func-
tion and pin compatible with the standard LS logic family.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



Texas Instruments CD74HCT368E
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Pinouts
CD54HC367, CD54HCT367
(CERDIP)
CD74HC367, CD74HCT367
(PDIP, SOIC)
TOP VIEW
OE1 1
1A 2
1Y 3
2A 4
2Y 5
3A 6
3Y 7
GND 8
16 VCC
15 OE2
14 6A
13 6Y
12 5A
11 5Y
10 4A
9 4Y
CD54HC368
(CERDIP)
CD74HC368, CD74HCT368
(PDIP, SOIC)
TOP VIEW
OE1 1
1A 2
1Y 3
2A 4
2Y 5
3A 6
3Y 7
GND 8
16 VCC
15 OE2
14 6A
13 6Y
12 5A
11 5Y
10 4A
9 4Y
Functional Diagrams
HC367, HCT367
1
OE1
2
1A
3
1Y
4
2A
5
2Y
6
3A
7
3Y
8
GND
16
VCC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
HC368, CD74HCT368
1
OE1
2
1A
3
1Y
4
2A
5
2Y
6
3A
7
3Y
8
GND
16
VCC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
TRUTH TABLE
INPUTS
OUTPUTS
(Y)
OE
A
HC/HCT367 HC/HCT368
L
L
L
H
L
H
H
L
H
X
(Z)
(Z)
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
2



Texas Instruments CD74HCT368E
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Logic Diagram
2
1A
ONE OF SIX IDENTICAL CIRCUITS
VCC
16
(NOTE 1)
3
1Y
GND
8
1
OE1
15
OE2
4
2A
6
3A
10
4A
12
5A
14
6A
5
2Y
7
3Y
9
4Y
11
5Y
13
6Y
NOTE:
1. Inverter not included in HC/HCT367
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3







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