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74HC574 Dataheets PDF



Part Number 74HC574
Manufacturers Texas Instruments
Logo Texas Instruments
Description Octal D-Type Flip-Flop
Datasheet 74HC574 Datasheet74HC574 Datasheet (PDF)

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered [ /Title (CD74 HC374 , CD74 HCT37 4, CD74 HC574 , CD74 HCT57 Features Description • Buffered Inputs • Common Three-State Output Enable Control • Three-State Outputs • Bus Line Driving Capability • Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA =.

  74HC574   74HC574


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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered [ /Title (CD74 HC374 , CD74 HCT37 4, CD74 HC574 , CD74 HCT57 Features Description • Buffered Inputs • Common Three-State Output Enable Control • Three-State Outputs • Bus Line Driving Capability • Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2-V to 6-V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5-V to 5.5-V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high-impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC374F3A -55 to 125 20 Ld CERDIP CD54HC574F3A -55 to 125 20 Ld CERDIP CD54HCT374F3A -55 to 125 20 Ld CERDIP CD54HCT574F3A -55 to 125 20 Ld CERDIP CD74HC374E -55 to 125 20 Ld PDIP CD74HC374M -55 to 125 20 Ld SOIC CD74HC374M96 -55 to 125 20 Ld SOIC CD74HC574E -55 to 125 20 Ld PDIP CD74HC574M -55 to 125 20 Ld SOIC CD74HC574M96 -55 to 125 20 Ld SOIC CD74HCT374E -55 to 125 20 Ld PDIP CD74HCT374M -55 to 125 20 Ld SOIC CD74HCT374M96 -55 to 125 20 Ld SOIC CD74HCT574E -55 to 125 20 Ld PDIP CD74HCT574M -55 to 125 20 Ld SOIC CD74HCT574M96 -55 to 125 20 Ld SOIC CD74HCT574PWR -55 to 125 20 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Pinouts CD54HC374, CD54HCT374 (CERDIP) CD74HC374, CD74HCT374 (PDIP, SOIC) TOP VIEW OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP CD54HC574, CD54HCT574 (CERDIP) CD74HC574 (PDIP, SOIC) CD74HCT574 (PDIP, SOIC, TSSOP) TOP VIEW OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TRUTH TABLE INPUTS OUTPUT OE CP Dn Qn L ↑ H H L ↑ L L L L X Q0 H X X Z H = High Level (Steady State) L = Low Level (Steady State) X= Don’t Care ↑= Transition from Low to High Level Q0= The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 2 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Information Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . . θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage.


54HCT374 74HC574 54HC574


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