D-TYPE LATCHES. CD54HCT373 Datasheet

CD54HCT373 LATCHES. Datasheet pdf. Equivalent

CD54HCT373 Datasheet
Recommendation CD54HCT373 Datasheet
Part CD54HCT373
Description OCTAL TRANSPARENT D-TYPE LATCHES
Feature CD54HCT373; CD54HCT373, CD74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS453B – FEBRUARY 200.
Manufacture etcTI
Datasheet
Download CD54HCT373 Datasheet




Texas Instruments CD54HCT373
CD54HCT373, CD74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS453B – FEBRUARY 2001 – REVISED MAY 2003
D 4.5-V to 5.5-V VCC Operation
D Wide Operating Temperature Range of
–55°C to 125°C
D Balanced Propagation Delays and
Transition Times
D Standard Outputs Drive Up To 10 LS-TTL
Loads
D Significant Power Reduction Compared to
LS-TTL Logic ICs
D Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT373 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
CD54HCT373 . . . F PACKAGE
CD74HCT373 . . . E OR M PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube
CD74HCT373E
CD74HCT373E
Tube
–55°C to 125°C SOIC – M
Tape and reel
CD74HCT373M
HCT373M
CD74HCT373M96
CDIP – F Tube
CD54HCT373F3A CD54HCT373F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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Texas Instruments CD54HCT373
CD54HCT373, CD74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS453B FEBRUARY 2001 REVISED MAY 2003
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE 1
LE 11
C1
3
1D
1D
2
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments CD54HCT373
CD54HCT373, CD74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS453B FEBRUARY 2001 REVISED MAY 2003
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX
TA = 55°C
TO 125°C
MIN MAX
TA = 40°C
TO 85°C
MIN MAX
UNIT
VCC
VIH
VIL
VI
VO
t/v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition rise or fall rate
4.5 5.5 4.5 5.5 4.5 5.5 V
2
2
2
V
0.8
0.8
0.8 V
VCC
VCC
500
VCC
VCC
500
VCC V
VCC V
500 ns
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN MAX
TA = 55°C
TO 125°C
MIN MAX
TA = 40°C
TO 85°C
MIN MAX
UNIT
VOH
VOL
II
IOZ
ICC
ICC
VI = VIH or VIL
IOH = 20 µA
IOH = 6 mA
4.4
4.5 V
3.98
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
0.1
4.5 V
0.26
VI = VCC or 0
5.5 V
±0.1
VO = VCC or 0
5.5 V
±0.5
VI = VCC or 0,
IO = 0
5.5 V
8
One input at VCC 2.1 V, Other inputs at 0 or VCC
4.5 V to
5.5 V
360
4.4
4.4
V
3.7
3.84
0.1
0.1
V
0.4
0.33
±1
±1 µA
±10
±5 µA
160
80 µA
490
450 µA
Ci
10
10
10 pF
Co
10
10
10 pF
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
HCT INPUT LOADING TABLE
INPUT UNIT LOAD
OE
1.5
Any D
0.4
LE
1
Unit load is ICC limit
specified in electrical
characteristics table (e.g.,
360 µA max at 25°C).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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