8-Input Multiplexer/Register. CD74HCT356E Datasheet

CD74HCT356E Multiplexer/Register. Datasheet pdf. Equivalent

CD74HCT356E Datasheet
Recommendation CD74HCT356E Datasheet
Part CD74HCT356E
Description 8-Input Multiplexer/Register
Feature CD74HCT356E; Semiconductor CD74HCT356 SCLS459A - June 2001 - Revised May 2003 High-Speed CMOS Logic 8-Input Mu.
Manufacture etcTI
Datasheet
Download CD74HCT356E Datasheet




Texas Instruments CD74HCT356E
Semiconductor
CD74HCT356
SCLS459A - June 2001 - Revised May 2003
High-Speed CMOS Logic
8-Input Multiplexer/Register, Three-State
Features
Description
• Edge-Triggered Data Flip-Flops
- Transparent Select Latches
• Buffered Inputs
• 3-State Complementary Outputs
• Bus Line Driving Capability
Typical Propagation
TA = 25oC
Delay:
VCC
=
5V,
CL
=
15pF,
- Clock to Output = 22ns
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH
The CD74HCT356 consists of data selectors/multiplexers that
select one of eight sources. The data select bits (S0, S1, and
S2) are stored in transparent latches that are enabled by a low
latch enable input (LE).
The data is stored in edge-triggered flip-flops that are
triggered by a low-to-high clock transition.
In both types the 3-state outputs are controlled by three
output-enable inputs (OE1, OE2, and OE3).
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD74HCT356E
-55 to 125
20 Ld PDIP
CD74HCT356M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
Pinout
CD74HCT356
(PDIP or SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CP 9
GND 10
20 VCC
19 Y
18 Y
17 OE3
16 OE2
15 OE1
14 S0
13 S1
12 S2
11 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



Texas Instruments CD74HCT356E
Functional Diagram
SELECT (NOTE 1)
S2
S1
S0
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
CD74HCT356
S0
14
S1
13
S2
12
8
D0
7
D1
6
D2
5
D3
4
D4
3
D5
2
D6
1
D7
19
Y
18
Y
11
LE
15
OE1
16
OE2
17
OE3
9
CP
TRUTH TABLE
INPUTS
CLOCK
CP
X
X
X
H or L
H or L
H or L
H or L
H or L
H or L
H or L
OUTPUT ENABLES
OE1
OE2
OE3
H
X
X
X
H
X
X
X
L
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
OUTPUTS
Y
Y
Z
Z
Z
Z
Z
Z
D0
D0
D0n
D0n
D1
D1
D1n
D1n
D2
D2
D2n
D2n
D3
D3
D3n
D3n
D4
D4
D4n
D4n
D5
D5
D5n
D5n
D6
D6
D6n
D6n
2



Texas Instruments CD74HCT356E
CD74HCT356
TRUTH TABLE (Continued)
INPUTS
SELECT (NOTE 1)
CLOCK
OUTPUT ENABLES
OUTPUTS
S2
S1
S0
CP
OE1
OE2
OE3
Y
Y
H
H
H
L
L
H
D7
D7
H
H
H
H or L
L
L
H
D7n
D7n
H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); = Transition from Low to High Level;
X = Don’t Care; Z = High-Impedance State (Off State); D0n...D7n = the level of steady-state inputs D0 through D7, respectively,
before the most recent low-to-high transition of data control.
NOTE:
1. This column shows the input address setup with LE low.
Block Diagram
15
OE1
16
OE2
17
OE3
9
CP
8
D0
7
D1
6
D2
5
D3
4
D4
3
D5
2
D6
1
D7
11
LE
14
S0
13
S1
12
S2
ENABLE LOGIC
D
A
1
T
O
A
F
8
R
E
S
G
E
I
L
S
E
T
C
E
T
R
O
S
R
AR
DE
DG
RI
ES
ST
SE
R
ADDRESS
DECODE
19
Y
18
Y
BUFFERS
3







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