CD74HCT390

Data sheet acquired from Harris Semiconductor SCHS185C September 1997 - Revised October 2003 CD74HC390, CD54HCT390, CD74HCT390 High-Speed CMOS Logic Dual Decade Ripple Counter [ /Title (CD74 HC390 , CD74 HCT39 0) /Subject (High Speed CMOS Features Description Two BCD Decade or Bi-Quinary Counters One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100 Two Master Reset Inputs to Clear Each Decade Counter Individually Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divideby-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used...