Ripple Counter. CD74HCT390M Datasheet

CD74HCT390M Counter. Datasheet pdf. Equivalent

CD74HCT390M Datasheet
Recommendation CD74HCT390M Datasheet
Part CD74HCT390M
Description Dual Decade Ripple Counter
Feature CD74HCT390M; Data sheet acquired from Harris Semiconductor SCHS185C September 1997 - Revised October 2003 CD74HC.
Manufacture etcTI
Datasheet
Download CD74HCT390M Datasheet




Texas Instruments CD74HCT390M
Data sheet acquired from Harris Semiconductor
SCHS185C
September 1997 - Revised October 2003
CD74HC390,
CD54HCT390, CD74HCT390
High-Speed CMOS Logic
Dual Decade Ripple Counter
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Two BCD Decade or Bi-Quinary Counters
• One Package Can Be Configured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
• Two Master Reset Inputs to Clear Each Decade
Counter Individually
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The CD74HC390 and ’HCT390 dual 4-bit decade ripple
counters are high-speed silicon-gate CMOS devices and are
pin compatible with low-power Schottky TTL (LSTTL). These
devices are divided into four separately clocked sections.
The counters have two divide-by-2 sections and two divide-
by-5 sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a com-
mon master reset (nMR). If the two master reset inputs (1MR
and 2MR) are used to simultaneously clear all 8 bits of the
counter, a number of counting configurations are possible
within one package. The separate clock inputs (nCP0 and
nCP1) of each section allow ripple counter or frequency divi-
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.
Each section is triggered by the High-to-Low transition of the
input pulses (nCP0 and nCP1).
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
input and nQ0 becomes the decade output.
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identified by the “1” and “2”
prefixes in the pin configuration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
Ordering Information
Pinout
CD54HCT390
(CERDIP)
CD74HC390, CD74HCT390
(PDIP, SOIC)
TOP VIEW
1CP0 1
1MR 2
1Q0 3
1CP1 4
1Q1 5
1Q2 6
1Q3 7
GND 8
16 VCC
15 2CP0
14 2MR
13 2Q0
12 2CP1
11 2Q1
10 2Q2
9 2Q3
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HCT390F3A
-55 to 125
16 Ld CERDIP
CD74HC390E
-55 to 125
16 Ld PDIP
CD74HC390M
-55 to 125
16 Ld SOIC
CD74HC390MT
-55 to 125
16 Ld SOIC
CD74HC390M96
-55 to 125
16 Ld SOIC
CD74HCT390E
-55 to 125
16 Ld PDIP
CD74HCT390M
-55 to 125
16 Ld SOIC
CD74HCT390MT
-55 to 125
16 Ld SOIC
CD74HCT390M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



Texas Instruments CD74HCT390M
CD74HC390, CD54HCT390, CD74HCT390
Functional Diagram
1 (15)
nCP0
2 (14)
nMR
÷2
COUNTER
3 (13)
nQ0
4 (12)
nCP1
GND = 8
VCC = 16
÷5
COUNTER
5 (11)
6 (10)
nQ1
nQ2
7 (9)
nQ3
TRUTH TABLE
INPUTS
CP
MR
ACTION
L
No Change
L
Count
X
H
All Qs Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
= Transition from Low to High Level, = Transition from High to Low.
BCD COUNT SEQUENCE FOR 1/2 THE 390
OUTPUTS
COUNT
Q0
Q1
Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
Output nQ0 connected to nCP1 with counter input on nCP0.
B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390
OUTPUTS
COUNT
Q0
Q1
Q2
Q3
0
L
L
L
L
1
L
H
L
L
2
L
L
H
L
3
L
H
H
L
4
L
L
L
H
5
H
L
L
L
6
H
H
H
L
7
H
L
H
L
8
H
H
H
L
9
H
L
L
H
Output nQ3 connected to nCP0 with counter input on nCP1.
2



Texas Instruments CD74HCT390M
Logic Diagram
4(12)
nCP1
1(15)
nCP0
2(14)
nMR
CD74HC390, CD54HCT390, CD74HCT390
Q
Φ
R
Q
Φ
R
Q
Φ
R
Q
Φ
R
VCC = 16
GND = 8
3(13)
nQ0
5(11)
nQ1
6(10)
nQ2
7(9)
nQ3
3







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