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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well defined performance and repeatability.
FEATURES
• 4 LVCMOS/LVTTL outputs • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL • Maximum output frequency: 350MHz • Output skew: 40ps (maximum) • Part-to-part skew: 700ps (maximum) • Additive phase jitter, RMS: 0.04ps (typical) • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
00
CLK nCLK
11
CLK_SEL
D Q
LE
OE
PIN ASSIGNMENT
GND 1 16 Q0
OE 2
1 5 VDDO
VDD 3
14 Q1
CLK_EN 4 13 GND
CLK 5 12 Q2
Q0
nCLK 6
1 1 VDDO
CLK_SEL 7 10 Q3
Q1
LVCMOS_CLK 8
9 GND
Q2
ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
Q3
G Package
Top View
8305AGI
REV. B SEPTEMBER 17, 2012 1
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
GND
Power
Power supply ground.
2
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
3
VDD
Power
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
4
CLK_EN
Input Pullup disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
5
CLK
Input Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup/ Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs.
7
CLK_SEL
Input Pullup When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
8
LVCMOS_CLK Input Pulldown LVCMOS / LVTTL clock input.
10, 12, 14, 16 Q3, Q2, Q1, Q0 Output
Clock outputs. LVCMOS / LVTTL interface levels.
11, 15
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol C
IN
RPULLUP RPULLDOWN
CPD
ROUT
Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF kΩ kΩ
11
pF
5
7
12
Ω
8305AGI
REV. B SEPTEMBER 17, 2012 2
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
1
0
0
LVCMOS_CLK
Disabled; LOW
1
0
1
CLK, nCLK
Disabled; LOW
1
1
0
LVCMOS_CLK
Enabled
1
1
1
CLK, nCLK
Enabled
0
X
X
HiZ
NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
nCLK CLK, LVCMOS_CLK
CLK_EN
Disabled
Enabled
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
8305AGI
REV. B SEPTEMBER 17, 2012 3
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89°C/W (0 lfpm) -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VDD
Core Supply Voltage
3.135 3.135
VDDO
Output Supply Voltage
2.375 1.65
IDD
Power Supply Current
IDDO
Output Supply Current
Typical 3.3 3.3 2.5 1.8
Maximum 3.465 3.465 2.625 1.95 21 5
Units V V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V.