Linear Regulator. uP7706ADC8 Datasheet

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uP7706ADC8 Datasheet
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Part uP7706ADC8
Description 3A Ultra Low Dropout Linear Regulator
Feature uP7706ADC8; uP7706 3A Ultra Low Dropout Linear Regulator General Description Features The uP7706 is a 3A ult.
Manufacture uPI Semiconductor
Datasheet
Download uP7706ADC8 Datasheet




uPI Semiconductor uP7706ADC8
uP7706
3A Ultra Low Dropout Linear Regulator
General Description
Features
The uP7706 is a 3A ultra low dropout linear regulator
specifically designed for motherboard and notebook
applications. This device works with dual supplies, a control
input for the control circuitry and a power input as low as
1.2V for providing current to output. The uP7706 delivers
high-current and ultra-low-drop output voltage as low as
0.8V for applications where VOUT is very close to VIN.
The uP7706 features comprehensive control and protection
functions: a power on reset (POR) circuit for monitoring
both control and power inputs for proper operation; an EN
input for enabling or disabling the device, a power OK with
time delay for indicating the output voltage status, a
foldback current limit function, and a thermal shutdown
function.
The uP7706 is available in PSOP-8 or VDFN6x5-8L
packages with very low thermal resistance.
Applications
† Desktop PCs, Notebooks, and Workstations
† Graphic Cards
† Low Voltage Logic Supplies
† Microprocessor and Chipset Supplies
† Split Plane Microprocessor Supplies
† Advanced Graphics Cards Supplies
† SoundCards and Auxiliary Power Supplies
† SMPS Post Regulators
† Works with 1.2~5.5V VIN
„ Adjustable Output Voltage, Down to 0.8V
„ 1.5% Initial Accuracy
„ Excellent Line and Load Regulation
† 3A Guaranteed Output Current
„ 200mV @ 2A Dropout Voltage
† Very Low On-Resistance
„ 100mtypical
† VOUT Pull Low Resistance when Disabled
† Low Reverse Leakage (Output to Input )
† VOUT Power OK Signal
† Fast Transient Response
† Low External Component Count
† Low Cost and Easy to Use
† Enable Pin
† Over Current and Over Temperature Protection
Ordering Information
Order Number Package Type
Remark
uP7706U8
PSOP-8
uP7706ADC8 VDFN6x5 - 8L
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are
100% matte tin (Sn) plating and suitable for use in SnPb
or Pb-free soldering processes.
Pin Configuration & Typical Application Circuit
POK
EN
VIN
CNTL
1
8
2
7
GND
3
6
4
5
PSOP-8
GND
FB
VOUT
NC
POK 1
EN 2
VIN 3
CNTL 4
GND
8 GND
7 FB
6 VOUT
5 NC
DFN6x5-8L
5VCC
C1
0.1uF
VIN
C2
22uF
CNTL
4
EN
2
POK
1
VIN
3
VOUT
6
FB
7
8
GND
R3
10K
R2
12.5K
R1
10K
VOUT
C4
option
C3
100uF
uPI Semiconductor Corp., http://www.upi-semi.com
1
Rev. F00, File Name: uP7706-DS-F0000



uPI Semiconductor uP7706ADC8
uP7706
Functional Pin Description
Pin No.
1
2
3
4
5
6
7
8
Exposed
Pad
Name Pin Function
POK
Power OK Indication. This pin is an open-drain output and is set high impedance once VOUT
reaches 92% of its rating voltage.
EN
Enable Input. Pulling this pin below 0.8V turns the regulator off, reducing the quiescent current
to a fraction of its operating value.
Input Voltage. This is the drain input to the power device that supply current to the output pin.
VIN
Large bulk capacitors with low ESR should be placed physically close to this pin o prevent the
input rail from dropping during large load transient. A 10uF ceramic capacitor is recommended
at this pin.
CNTL
NC
Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and
driver for the pass transistor.The driving capability of output current is proportioned to the VCNTL.
For the device to regulate, the voltage on this pin must be at least 1.5V greater than the output
voltage, and no less than VCNTL_MIN.
Not Internally Connected.
Output Voltage. This pin is power output of the device. A pull low resistance exists when the
VOUT
device is disabled by pulling low the EN pin. To maintain adequate transient response to large
load change, typical value of 1000uF Al electrolytic capacitor with 10uF ceramic capacitors are
recommended to reduce the effects of current transients on VOUT.
FB
GND
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
the output to GND is used to set the regulation voltage as VOUT = 0.8x(R1+R2)/R1 (V)
Ground.
GND
Ground. The exposed pad acts the dominant power dissipation path and should be soldered
to well design PCB pads as described in the Application Informations Chapter.
Functional Block Diagram
EN
CNTL
VIN
2
4
3
Thermal Limit
0.3V
Softstart &
Control Logic
Power On
Reset
Current Limit
FB 7
0.8V VREF
6
92% VREF
Delay
1
POK
8
GND
uPI Semiconductor Corp., http://www.upi-semi.com
2
Rev. F00, File Name: uP7706-DS-F0000



uPI Semiconductor uP7706ADC8
uP7706
Functional Description
Definitions
Some important terminologies for LDO are specified below.
Dropout Voltage
The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Measured when the output drops
2% below its nominal value. Dropout voltage is affected by
junction temperature, load current and minimum input
supply requirements.
Line Regulation
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significantly affected.
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affected.
Maximum Power Dissipation
The maximum total device dissipation for which the
regulator will operate within specifications.
Initialization
The uP7706 automatically initiates upon the receipt of
supply voltage and power voltage. A power on reset circuit
continuously monitors VIN and CNTL pins voltages with
rising threshold levels of 1.0V and 2.7V respectively.
Chip Enable and Soft Start
It’s recommended to maintain 50-100uA through the output
divider network for a tight load and line regulation. The
internal voltage reference is VREF = 0.8V with 1.5%
accuracy over full temperature range. This commands the
use of 0.5% or better accuracy resistors to build a precision
power supply.
5VCC
C1
0.1uF
VIN
C2
22uF
CNTL
4
EN
2
POK
1
VIN
3
VOUT
6
FB
7
8
GND
R3
10K
R2
12.5K
R1
10K
VOUT
C4
option
C3
100uF
Figure 1. Typical application of 2.5V to 1.8V conversion
with a 5.0V control supply
Over Current Protection
The uP7706 features a foldback over current protection
function as shown in Figure 2. The current limit threshold
level is proportional to VOUT/VNOM and is typically 4A when
VOUT = VNOM, where VNOM is the target output voltage. If the
output continuously demands more current than the
maximum current, output voltage will eventually drops below
its nominal value. This, in turns, will lower its OCP threshold
level. This will limit power dissipation in the device when
over current limit happens. The power dissipation is near
zero when the output is short circuited to ground.
The uP7706 features an enable pin for enable/disable
control of the chip. Pulling VEN lower than 0.8V disables
the chip and reduces its quiescent current down to 1uA.
When disabled, an internal MOSFET of 90RDS(ON) turns
on to pull output voltage to ground. Pulling VEN higher than
2.0V enables the output voltage, providing POR is
recognized. The uP7706 features soft start function that
limits inrush current for charging the output capacitors. The
soft start time is typically 2.5ms.
Output Voltage Programming
Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
is sensed through a voltage divider and regulated to internal
reference voltage VREF. The output voltage is programmed
as:
VOUT = VREF x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V
3V VOUT
2A
1V
IOUT
0A
1A
2A
3A
4A
Figure 2. Current Limit Behavior
uPI Semiconductor Corp., http://www.upi-semi.com
3
Rev. F00, File Name: uP7706-DS-F0000







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