1-megabit DataFlash. AT45D011 Datasheet

AT45D011 DataFlash. Datasheet pdf. Equivalent

AT45D011 Datasheet
Recommendation AT45D011 Datasheet
Part AT45D011
Description 1-megabit DataFlash
Feature AT45D011; Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation – Sing.
Manufacture ATMEL
Datasheet
Download AT45D011 Datasheet




ATMEL AT45D011
Features
Single 4.5V - 5.5V Supply
Serial Interface Architecture
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
One 264-byte SRAM Data Buffer
Internal Program and Control Timer
Fast Page Program Time – 7 ms Typical
120 µs Typical Page to Buffer Transfer Time
Low Power Dissipation
– 15 mA Active Read Current Typical
– 10 µA CMOS Standby Current Typical
15 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT45D011 is a 5.0-volt only, serial interface Flash memory suitable for in-system
reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264
bytes each. In addition to the main memory, the AT45D011 also contains one SRAM
data buffer of 264 bytes. Unlike conventional Flash memories that are accessed
randomly with multiple address lines and a parallel interface, the DataFlash uses a
Pin Configurations
Pin Name
CS
SCK
SI
Function
Chip Select
Serial Clock
Serial Input
SOIC
(continued)
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
SO
Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY Ready/Busy
PLCC
TSSOP Top View
Type 1
SCK 5
SI 6
SO 7
NC 8
NC 9
NC 10
NC 11
NC 12
NC 13
29 WP
28 RESET
27 RDY/BUSY
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
RDY/BUSY 1
RESET 2
WP 3
VCC 4
GND 5
SCK 6
SO 7
14 CS
13 NC
12 NC
11 NC
10 NC
9 NC
8 SI
1-megabit
5.0-volt Only
Serial
DataFlash®
AT45D011
Recommend using
AT45DB011B for new
designs.
AT45DB011
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
Note: PLCC package pins 16
and 17 are DONT CONNECT
Rev. 1123C–01/01
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ATMEL AT45D011
serial interface to sequentially access its data. The simple
serial interface facilitates hardware layout, increases sys-
tem reliability, minimizes switching noise, and reduces
package size and active pin count. The device is optimized
for use in many commercial and industrial applications
where high density, low pin count, low voltage, and low
power are essential. Typical applications for the DataFlash
are digital voice storage, image storage, and data storage.
The device operates at clock frequencies up to 15 MHz
with a typical active read current consumption of 15 mA.
To allow for simple in-system reprogrammability, the
AT45D011 does not require high input voltages for
programming. The device operates from a single power
supply, 4.5V to 5.5V, for both the program and read opera-
tions. The AT45D011 is enabled through the chip select pin
(CS) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the
AT45D011 is divided into three levels of granularity com-
prising of sectors, blocks, and pages. The Memory
Architecture Diagram illustrates the breakdown of each
level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page
by page basis; however, the optional erase operations can
be performed at the block or page level.
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AT45D011



ATMEL AT45D011
AT45D011
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 2112 BYTES (2K + 64)
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
SECTOR 1 = 65,472 BYTES (62K + 1984)
BLOCK 29
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
8 Pages
SECTOR 2 = 67,584 BYTES (64K + 2K)
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 61
BLOCK 62
BLOCK 63
Block = 2112 bytes
(2K + 64)
PAGE 509
PAGE 510
PAGE 511
Page = 264 bytes
(256 + 8)
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from the data buffer.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 512
pages in the main memory, bypassing the data buffer and
leaving the contents of the buffer unchanged. To start a
page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 dont care bits. In the AT45D011, the
first six address bits are reserved for larger density devices
(see Notes on page 10), the next nine address bits (PA8-
PA0) specify the page address, and the next nine address
bits (BA8-BA0) specify the starting byte address within the
page. The 32 dont care bits which follow the 24 address
bits are sent to initialize the read operation. Following the
32 dont care bits, additional pulses on SCK result in serial
data being output on the SO (serial output) pin. The CS pin
must remain low during the loading of the opcode, the
address bits, and the reading of data. When the end of a
page in main memory is reached during a main memory
page read, the device will continue reading at the beginning
of the same page. A low-to-high transition on the CS pin
will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer
using an opcode of 54H. To perform a buffer read, the eight
bits of the opcode must be followed by 15 dont care bits,
nine address bits, and eight dont care bits. Since the buffer
size is 264-bytes, nine address bits (BFA8-BFA0) are
required to specify the first byte of data to be read from the
buffer. The CS pin must remain low during the loading of
the opcode, the address bits, the dont care bits, and the
reading of data. When the end of the buffer is reached, the
device will continue reading back at the beginning of the
buffer. A low-to-high transition on the CS pin will terminate
the read operation and tri-state the SO pin.
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