Operational Amplifier. LMC662AIN Datasheet

LMC662AIN Amplifier. Datasheet pdf. Equivalent

LMC662AIN Datasheet
Recommendation LMC662AIN Datasheet
Part LMC662AIN
Description CMOS Dual Operational Amplifier
Feature LMC662AIN; LMC662 www.ti.com SNOSC51C – APRIL 1998 – REVISED MARCH 2013 LMC662 CMOS Dual Operational Amplifi.
Manufacture etcTI
Datasheet
Download LMC662AIN Datasheet




Texas Instruments LMC662AIN
LMC662
www.ti.com
SNOSC51C – APRIL 1998 – REVISED MARCH 2013
LMC662 CMOS Dual Operational Amplifier
Check for Samples: LMC662
FEATURES
1
2 Rail-to-Rail Output Swing
• Specified for 2 kΩ and 600Ω Loads
• High Voltage Gain: 126 dB
• Low Input Offset Voltage: 3 mV
• Low Offset Voltage Drift: 1.3 μV/°C
• Ultra Low Input Bias Current: 2 fA
• Input Common-Mode Range Includes V
• Operating Range from +5V to +15V Supply
• ISS = 400 μA/amplifier; Independent of V+
• Low Distortion: 0.01% at 10 kHz
• Slew Rate: 1.1 V/μs
APPLICATIONS
• High-Impedance Buffer or Preamplifier
• Precision Current-to-Voltage Converter
• Long-Term Integrator
• Sample-and-Hold Circuit
• Peak Detector
• Medical Instrumentation
• Industrial Controls
• Automotive Sensors
DESCRIPTION
The LMC662 CMOS Dual operational amplifier is
ideal for operation from a single supply. It operates
from +5V to +15V and features rail-to-rail output
swing in addition to an input common-mode range
that includes ground. Performance limitations that
have plagued CMOS amplifiers in the past are not a
problem with this design. Input VOS, drift, and
broadband noise as well as voltage gain into realistic
loads (2 kΩ and 600Ω) are all equal to or better than
widely accepted bipolar equivalents.
This chip is built with TI's advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC660 datasheet for a Quad CMOS
operational amplifier with these same features.
Connection Diagram
Typical Application
Figure 1. 8-Pin PDIP, SOIC
Figure 2. Low-Leakage Sample-and-Hold
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated



Texas Instruments LMC662AIN
LMC662
SNOSC51C – APRIL 1998 – REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings(1)(2)(3)
Differential Input Voltage
Supply Voltage (V+ V)
Output Short Circuit to V+
Output Short Circuit to V
Lead Temperature
(Soldering, 10 sec.)
Storage Temp. Range
Voltage at Input/Output Pins
Current at Output Pin
Current at Input Pin
Current at Power Supply Pin
Power Dissipation
Junction Temperature
ESD Tolerance(7)
±Supply Voltage
16V
See (4)
See (5)
260°C
65°C to +150°C
(V+) +0.3V, (V) 0.3V
±18 mA
±5 mA
35 mA
See (6)
150°C
1000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) A military RETS electrical test specification is available on request.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(6) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)/θJA.
(7) Human body model, 1.5 kΩ in series with 100 pF.
Operating Ratings(1)
Temperature Range
LMC662AI
LMC662C
Supply Voltage Range
Power Dissipation
Thermal Resistance (θJA)(3)
8-Pin PDIP
8-Pin SOIC
40°C TJ +85°C
0°C TJ +70°C
4.75V to 15.5V
See (2)
101°C/W
165°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA.
(3) All numbers apply for packages soldered directly into a PC board.
2
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Copyright © 1998–2013, Texas Instruments Incorporated



Texas Instruments LMC662AIN
LMC662
www.ti.com
SNOSC51C – APRIL 1998 – REVISED MARCH 2013
DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V=
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
Parameter
Test Conditions
Typ (1)
LMC662AI
Limit (1)
LMC662C
Limit (1)
Units
Input Offset Voltage
1
3
6
mV
3.3
6.3
max
Input Offset Voltage
Average Drift
1.3
μV/°C
Input Bias Current
0.002
pA
4
2
max
Input Offset Current
0.001
pA
2
1
max
Input Resistance
>1
TeraΩ
Common Mode
Rejection Ratio
Positive Power Supply
0V VCM 12.0V
V+ = 15V
5V V+ 15V
83
70
63
dB
68
62
min
83
70
63
dB
Rejection Ratio
Negative Power Supply
VO = 2.5V
0V V≤ −10V
68
62
min
94
84
74
dB
Rejection Ratio
Input Common-Mode
V+ = 5V & 15V
83
73
min
0.4
0.1
0.1
V
Voltage Range
Large Signal
Voltage Gain
For CMRR 50 dB
RL = 2 kΩ (2)
Sourcing
V+ 1.9
2000
0
V+ 2.3
V+ 2.5
440
400
0
V+ 2.3
V+ 2.4
300
200
max
V
min
V/mV
min
Sinking
500
180
90
V/mV
RL = 600Ω (2)
Sourcing
120
1000
220
200
80
min
150
V/mV
100
min
Output Swing
Sinking
V+ = 5V
RL = 2 kΩ to V+/2
100
250
60
50
V/mV
40
min
4.87
4.82
4.78
V
4.79
4.76
min
0.10
0.15
0.19
V
V+ = 5V
RL = 600Ω to V+/2
0.17
0.21
max
4.61
4.41
4.27
V
4.31
4.21
min
0.30
0.50
0.63
V
V+ = 15V
RL = 2 kΩ to V+/2
14.63
0.26
0.56
14.50
14.44
0.35
0.69
max
14.37
V
14.32
min
0.44
V
V+ = 15V
RL = 600Ω to V+/2
13.90
0.79
0.40
13.35
13.15
1.16
0.48
max
12.92
V
12.76
min
1.45
V
1.32
1.58
max
(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
(2) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V.
Copyright © 1998–2013, Texas Instruments Incorporated
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