Flash Memory. PM49FL004T Datasheet

PM49FL004T Memory. Datasheet pdf. Equivalent

PM49FL004T Datasheet
Recommendation PM49FL004T Datasheet
Part PM49FL004T
Description 4-Mbit Fimware Hub / LPC Flash Memory
Feature PM49FL004T; Pm49FL002 / Pm49FL004 2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory FEATURES • Single.
Manufacture Programmable Microelectronics
Datasheet
Download PM49FL004T Datasheet




Programmable Microelectronics PM49FL004T
Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
FEATURES
• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Interface
- Read compatible to Intel® 82802 Firmware Hub
devices
- Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
- Pm49FL002: 256K x 8 (2 Mbit)
- Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
- Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Top Boot Block
- Pm49FL002: 16 Kbyte top Boot Block
- Pm49FL004: 64 Kbyte top Boot Block
Automatic Erase and Program Operation
- Build-in automatic program verification for
extended product endurance
- Typical 25 µs/byte programming time
- Typical 50 ms sector/block/chip erase time
Two Configurable Interfaces
- In-System hardware interface: Auto detection of
Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle for in-system read and write
operations
- Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
Firmware HUB (FWH)/Low Pin Count (LPC)
Mode
- 33 MHz synchronous operation with PCI bus
- 5-signal communication interface for in-system
read and write operations
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
- Register-based read and write protection for
each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
(FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot
Block
- WP# pin for hardware write protection to whole
memory array except Boot Block
Address/Address Multiplexed (A/A Mux)
Mode
- 11-pin multiplexed address and 8-pin data I/O
interface
- Supports fast programming on EPROM
programmers
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
Lower Power Consumption
- Typical 2 mA active read current
- Typical 7 mA program/erase current
High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
Compatible Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional Halogen-free package
Hardware Data Protection
Chingis Technology Corporation
1
P-Flash is registered trademark of Chingis Technology Corporation.
Intel is a registered trademark of Intel Corporation.
Issue Date: April, 2009 Rev:2.0



Programmable Microelectronics PM49FL004T
Pm49FL002 / 004
GENERAL DESCRIPTION
The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These
devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-
system or off-system read, erase and program operations. The 12.0 Volt VPP power supply are not required for the
program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification
revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications.
The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic de-
tect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/
A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both
Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great
flexibility and simplicity for design, procurement, and material inventory.
The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector
group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,
or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature
allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase
operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one
single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-
tion.
The program operation of Pm49FL002/004 is executed by issuing the program command code into command
register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase
operation of the devices is executed by issuing the sector, block, or chip erase command code into command
register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming
on the array which has not been programmed is not required before an erase operation. The devices offer Data#
Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and
erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.
The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The
Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled
by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The
rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers
(FWH mode only).
The Pm49FL002/004 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices are offered in
32-pin VSOP and PLCC packages with optional environmental friendly Halogen-free package.
Chingis Technology Corporation
2
Issue Date: April, 2009 Rev: 2.0



Programmable Microelectronics PM49FL004T
CONNECTION DIAGRAMS
Pm49FL002 / 004
FWH
GPI1
GPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0
LPC
GPI1
GPI0
WP#
TBL#
RES
RES
RES
RES
LAD0
A/A Mux
A7 5
43
A/A Mux LPC FWH
2 1 32 31 30
29 IC
IC
IC
A6 6
28 GND GND
GND
A5 7
27 NC NC
NC
A4 8
26 NC NC
NC
A3
A2
A1
A0
I/O0
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
VCC
VCC
VCC
OE#
WE#
INIT# INIT#
LFRAME# FWH4
NC NC
NC
I/O7 RES
RES
32-PIN PLCC
FWH LPC A/A Mux
NC NC NC
1
NC
NC NC
2
NC
NC NC
3
GND GND GND
4
IC
IC
IC
5
GPI4 GPI4 A10
6
CLK CLK R/C#
7
VCC
VCC
VCC
8
NC
NC NC
9
RST# RST# RST#
10
GPI3 GPI3
A9
11
GPI2 GPI2
A8
12
GPI1 GPI1
A7
13
GPI0 GPI0
A6
14
WP# WP# A5
15
TBL# TBL# A4
16
A/A Mux LPC FWH
32
OE# INIT#
INIT#
31
WE# LFRAME# FWH4
30
NC NC
NC
29
I/O7 RES
RES
28
I/O6 RES
RES
27
I/O5 RES
RES
26
I/O4 RES
RES
25
I/O3 LAD3 FWH3
24
GND GND
GND
23
I/O2 LAD2 FWH2
22
I/O1 LAD1 FWH1
21
I/O0 LAD0 FWH0
20
A0
RES
ID0
19
A1
RES
ID1
18
A2
RES
ID2
17
A3
RES
ID3
Chingis Technology Corporation
32-PIN (8mm x 14mm) VSOP
3
Issue Date: April, 2009 Rev: 2.0







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)