SN74ACT1071

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . . IFRM = 100 mA Inputs Are TTL-Voltage Compatible Low Power Consumption (Like CMOS) ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 D PACKAGE (TOP VIEW) D1 1 D2 2 GND 3 GND 4 D3 5 D4 6 D5 7 14 D10 13 D9 12 D8 11 VCC 10 VCC 9 D7 8 D6 description This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1071 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state. The SN74ACT1071 is characterized for operation from ...