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SN74ACT1071D Dataheets PDF



Part Number SN74ACT1071D
Manufacturers Texas Instruments
Logo Texas Instruments
Description 10-BIT BUS-TERMINATION ARRAY
Datasheet SN74ACT1071D DatasheetSN74ACT1071D Datasheet (PDF)

• Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems • Reduces Undershoot and Overshoot Caused By Line Reflections • Repetitive Peak Forward Current . . . IFRM = 100 mA • Inputs Are TTL-Voltage Compatible • Low Power Consumption (Like CMOS) • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise SN74ACT1071 10-BIT BUS-TERMINATION A.

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• Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems • Reduces Undershoot and Overshoot Caused By Line Reflections • Repetitive Peak Forward Current . . . IFRM = 100 mA • Inputs Are TTL-Voltage Compatible • Low Power Consumption (Like CMOS) • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 D PACKAGE (TOP VIEW) D1 1 D2 2 GND 3 GND 4 D3 5 D4 6 D5 7 14 D10 13 D9 12 D8 11 VCC 10 VCC 9 D7 8 D6 description This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1071 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state. The SN74ACT1071 is characterized for operation from – 40°C to 85°C. logic diagram, one of ten channels (positive logic) D1 1 VCC 11 VCC 10 TG GND 3 4 GND PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 4–1 SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Continuous input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Positive-peak input clamp current, IIK (VI > VCC) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . 100 mA Negative-peak input clamp current, IIK (VI < 0) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . . –100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed. recommended operating conditions VCC VIH VIL VI TA Supply voltage High-level input voltage Low-level input voltage Input voltage Operating free-air temperature MIN MAX UNIT 4.5 5.5 V 2.5 V 0.8 V 0 VCC V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN TYP† MIN MAX MAX UNIT IIL VCC = 4.5 to 5.5 V, VI = 0.8 V 0.15 0.3 0.9 0.1 1 mA IIH VCC = 4.5 to 5.5 V, VI = 2.5 V – 0.2 – 0.5 –1.4 – 0.15 –1.5 mA VIKL IIN = –18 mA –1.5 –1.5 V VIKH ICC‡ ∆ICC§ IIN = 18 mA VCC = 5.5 V, One input at 3.4 V, Inputs open Other inputs at VCC or GND VCC + 2 4 0.9 VCC + 2 V 40 µA 1 mA Ci VI = VCC or GND 3 pF † All typical values are at VCC = 5 V. ‡ Inputs may be set high or low prior to the ICC measurement. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. 4–2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 IF – Forward Current – mA SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 TYPICAL CHARACTERISTICS FORWARD CURRENT vs INPUT VOLTAGE (UPPER CLAMPING DIODE) 60 55 50 45 40 35 30 25 20 15 10 5 0 5.5 6 6.5 7 7.5 8 VI – Input Voltage – V 8.5 9 Figure 1 IF – Forward Current – mA FORWARD CURRENT vs INPUT VOLTAGE (LOWER CLAMPING DIODE) 5 0.


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