SN74ACT1284PW

SN54ACT1284, SN74ACT1284 7ĆBIT BUS INTERFACES WITH 3ĆSTATE OUTPUTS SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 20 ns at 5 V D 3-State Outputs Directly Drive Bus Lines D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) D Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications description/ordering information SN54ACT1284 . . . J OR W PACKAGE SN74ACT1284 . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW) A1 1 A2 2 A3 3 A4 4 GND 5 GND 6 A5 7 A6 8 A7 9 DIR 10 20 B1 19 B2 18 B3 17 B4 16 VCC 15 VCC 14 B5 13 B6 12 B7 11 HD SN54ACT1284 . . . FK PACKAGE (TOP VIEW) B2 B1 A1 A2 A3 The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements. The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction. A7 DIR HD A4 GND GND A5 A6 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 B3 B4 VCC VCC B5 B7 B6 The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the hi...