BUS INTERFACE. SNJ54ACT1284W Datasheet

SNJ54ACT1284W INTERFACE. Datasheet pdf. Equivalent

SNJ54ACT1284W Datasheet
Recommendation SNJ54ACT1284W Datasheet
Part SNJ54ACT1284W
Description 7-BIT BUS INTERFACE
Feature SNJ54ACT1284W; SN54ACT1284, SN74ACT1284 7ĆBIT BUS INTERFACES WITH 3ĆSTATE OUTPUTS SCAS459D − NOVEMBER 1994 − REVISE.
Manufacture etcTI
Datasheet
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Texas Instruments SNJ54ACT1284W
SN54ACT1284, SN74ACT1284
7ĆBIT BUS INTERFACES
WITH 3ĆSTATE OUTPUTS
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
D 4.5-V to 5.5-V VCC Operation
D Inputs Accept Voltages to 5.5 V
D Max tpd of 20 ns at 5 V
D 3-State Outputs Directly Drive Bus Lines
D Flow-Through Architecture Optimizes PCB
Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D Designed for the IEEE 1284-I (Level-1 Type)
and IEEE 1284-II (Level-2 Type) Electrical
Specifications
description/ordering information
SN54ACT1284 . . . J OR W PACKAGE
SN74ACT1284 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
A1 1
A2 2
A3 3
A4 4
GND 5
GND 6
A5 7
A6 8
A7 9
DIR 10
20 B1
19 B2
18 B3
17 B4
16 VCC
15 VCC
14 B5
13 B6
12 B7
11 HD
SN54ACT1284 . . . FK PACKAGE
(TOP VIEW)
The ’ACT1284 devices are designed for
asynchronous two-way communication between
data buses. The control function minimizes
external timing requirements.
The devices allow data transmission in either the
A-to-B or the B-to-A direction for bits 1, 2, 3, and
4, depending on the logic level at the
direction-control (DIR) input. Bits 5, 6, and 7,
however, always transmit in the A-to-B direction.
A4
GND
GND
A5
A6
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B3
B4
VCC
VCC
B5
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the
drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel
peripheral-interface specification.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74ACT1284DW
SN74ACT1284DWR
ACT1284
0°C to 70°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74ACT1284NSR
SN74ACT1284DBR
ACT1284
AU284
TSSOP − PW
Tube
Tape and reel
SN74ACT1284PW
SN74ACT1284PWR
AU284
CDIP − J
Tube
SNJ54ACT1284J
SNJ54ACT1284J
−55°C to 125°C CFP − W
Tube
SNJ54ACT1284W
SNJ54ACT1284W
LCCC − FK
Tube
SNJ54ACT1284FK
SNJ54ACT1284FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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Texas Instruments SNJ54ACT1284W
SN54ACT1284, SN74ACT1284
7ĆBIT BUS INTERFACES
WITH 3ĆSTATE OUTPUTS
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
INPUTS
DIR HD
L
L
L
H
H
L
H
H
FUNCTION TABLE
OUTPUT
Open drain
Totem pole
Totem pole
Open drain
Totem pole
MODE
A to B: Bits 5, 6, 7
B to A: Bits 1, 2, 3, 4
B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
logic diagram (positive logic)
HD
DIR
A1, A2, A3, A4
A5, A6, A7
B1, B2, B3, B4
B5, B6, B7
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SNJ54ACT1284W
SN54ACT1284, SN74ACT1284
7ĆBIT BUS INTERFACES
WITH 3ĆSTATE OUTPUTS
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
B-port input and output voltage range, VI and VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . −2 V to 7 V
A-port input and output voltage range, VI and VO (see Note 1) . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 20 ns if the input voltage goes more negative than −0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54ACT1284 SN74ACT1284
UNIT
MIN MAX MIN MAX
VCC
VIH
VIL
VI
VO
IOH
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Open-drain output voltage
High-level output current
HD low
B port, HD high
A port
4.7 5.5
2
0.8
0 VCC
0 5.5
−14
−4
4.7 5.5 V
2
V
0.8 V
0 VCC V
0 5.5 V
−14
mA
−4
IOL
Low-level output current
B port
A port
14
14
mA
4
4
TA
Operating free-air temperature
−55 125
0
70 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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