EDGE-TRIGGERED FLIP-FLOP. SN74ACT16374-EP Datasheet

SN74ACT16374-EP FLIP-FLOP. Datasheet pdf. Equivalent

SN74ACT16374-EP Datasheet
Recommendation SN74ACT16374-EP Datasheet
Part SN74ACT16374-EP
Description 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
Feature SN74ACT16374-EP; SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – R.
Manufacture etcTI
Datasheet
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Texas Instruments SN74ACT16374-EP
SN74ACT16374Q-EP
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS679B – MAY 2002 – REVISED JULY 2002
D Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
–40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree
D Member of the Texas Instruments
WidebusFamily
D Inputs Are TTL-Voltage Compatible
D 3-State Bus Driving True Outputs
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, highly
accelerated stress test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
description
The SN74ACT16374Q-EP is a 16-bit
edge-triggered D-type flip-flop with 3-state
outputs, designed specifically for driving highly
capacitive or relatively low-impedance loads. It is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
VCC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
VCC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
An output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system,
without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 125°C SSOP – DL
Tape and reel SN74ACT16374QDLREP ACT16374QEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1



Texas Instruments SN74ACT16374-EP
SN74ACT16374Q-EP
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS679B MAY 2002 REVISED JULY 2002
FUNCTION TABLE
(each section)
INPUTS
OE CLK D
OUTPUT
Q
L
H
H
L
L
L
L H or L X
Q0
H
X
X
Z
logic diagram (positive logic)
1
1OE
48
1CLK
2OE 24
25
2CLK
47
1D1
C1
1D
2
1Q1
2D1 36
C1
1D
13
2Q1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±260 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN74ACT16374-EP
SN74ACT16374Q-EP
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS679B MAY 2002 REVISED JULY 2002
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC
VIH
VIL
VI
VO
IOH
IOL
Dt/Dv
Supply voltage (see Note 4)
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
4.5
5 5.5 V
2
V
0.8 V
0
VCC V
0
VCC V
16 mA
16 mA
0
10 ns/V
TA
NOTES:
Operating free-air temperature
40
125 °C
3. All unused inputs of the device must be at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. All VCC and GND pins must be connected to the proper-voltage power supply.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN TYP MAX
MIN MAX
IOH = 50 mA
4.5 V 4.4
4.4
5.5 V 5.4
5.4
VOH
IOH = 16 mA
4.5 V 3.94
3.7
5.5 V 4.94
4.7
IOH = 24 mA{
5.5 V
3.85
IOL = 50 mA
4.5 V
5.5 V
0.1
0.1
0.1
0.1
VOL
IOL = 16 mA
4.5 V
5.5 V
0.36
0.5
0.36
0.5
IOL = 24 mA{
5.5 V
0.5
II
IOZ
ICC
DICC
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
IO = 0
Other inputs at GND or VCC
5.5 V
5.5 V
5.5 V
5.5 V
±0.1
±1
±0.5
±10
8
160
0.9
1
Ci
VI = VCC or GND
5V
4.5
Co
VO = VCC or GND
5V
12
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL-voltage levels rather than 0 V to VCC.
UNIT
V
V
mA
mA
mA
mA
pF
pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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