Correction Controller. CS1501 Datasheet

CS1501 Controller. Datasheet pdf. Equivalent

CS1501 Datasheet
Recommendation CS1501 Datasheet
Part CS1501
Description Digital Power Factor Correction Controller
Feature CS1501; CS1501 Digital Power Factor Correction Control IC Features  Digital EMI Noise Shaping  Adaptive .
Manufacture Cirrus Logic
Datasheet
Download CS1501 Datasheet




Cirrus Logic CS1501
CS1501
Digital Power Factor Correction Control IC
Features
Digital EMI Noise Shaping
Adaptive Digital Energy Controller
• Excellent Efficiency Under All Load and Line Conditions
• Zero-voltage Switching Topology
Minimal External Devices Required
Adaptive Digital Control Loop
Comprehensive Safety Features
• Undervoltage Lockout (UVLO)
• Output Overvoltage Protection
• Cycle-by-cycle Current Limiting
• Open/Short Loop Protection for IAC & IFB Pins
• Thermal Shutdown
Pin Placement Similar to Traditional Boundary Mode (CRM)
Controllers
Overview
The CS1501 is a high-performance digital power factor
correction (PFC) controller designed for switching mode power
supply (SMPS) applications. The CS1501 actively manages
the power factor correction while achieving high efficiency over
a wide load range.
The CS1501 adaptively controls the input AC current so that it
is in phase with the AC mains voltage, and its waveform mimics
the input voltage waveform. The PFC controller executes
adaptive digital algorithms designed to shape the AC mains
input current waveform to be in phase with the input voltage
waveform.
The CS1501 is equipped with a zero-current detection (ZCD)
circuit providing the PFC digital controller the capability to turn
on the MOSFET when the voltage across the drain and source
is near zero. Additionally, a current-sensing circuit is
incorporated for instantaneous overcurrent protection.
Applications
LCD and LED TVs
Notebooks
Server/Telecom
Ordering Information
See page 16.
BR1
AC
Mains
BR 1
Vr e c t
LB
BR1
R1
VDD
R5
R2
C1
R6
R3
8
1
5 ZCD
VDD IFB
GD 7
CS1501
3 IAC
CS 4
BR 1
STBY GND
R4
2
6
D1
Vlink
Q1
C2 Regulated
DC Output
R7
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
FEB’12
DS927F4



Cirrus Logic CS1501
CS1501
1. INTRODUCTION
VDD
STBY 2
600k
VDD
IFB 1
15k
24k
VDD
IAC 3
15k
24k
Iref
ADC
Iref
ADC
tLEB
CS 600
4
VCS (th)
-
+
VCS (clamp )
+
-
CS
Threshold
CS Clamp
VDD
Voltage
Regulator
POR
+
-
VDD ( on)
VZ
VDD ( off)
8 VDD
7 GD
tZCB
6 GND
Zero Crossing
Detect
+
- V ZCD(th )
5 ZCD
Figure 1. CS1501 Block Diagram
The CS1501 digital power factor correction (PFC) control IC is
designed to deliver the lowest system cost by reducing the
total number of system components and optimizing the EMI
noise signature, which reduces the conducted EMI filter
requirements. The CS1501 digital algorithm determines the
behavior of the boost converter during startup, normal
operation, and under fault conditions (overvoltage,
overcurrent, and overtemperature).
Figure 1 illustrates a high-level block diagram of the CS1501.
The PFC processor logic regulates the power transfer by
using an adaptive digital algorithm to optimize the PFC
active-switch (MOSFET) drive signal duty cycle and switching
frequency. The adaptive controller uses independent
analog-to-digital converter (ADC) channels when sensing the
feedback and feedforward analog signals required to
implement the digital PFC control algorithm.
The AC mains rectified voltage (on pin IAC) and PFC output
link voltage (on pin IFB) are transformed by the PFC
processor logic and used to generate the optimum PFC
active-switch drive signal (GD) by calculating the optimal
switching frequency and tON time on a cycle-by-cycle basis.
An auxiliary winding is typically added to the PFC boost
inductor to provide zero-current detection (ZCD) information.
The ZCD acts as a demagnetization sensor used to monitor
the PFC active-switching behavior and efficiency. The
auxiliary voltage is normalized using an external attenuator
and is connected to the ZCD pin, providing the CS1501 a
mechanism to detect the valley/zero crossings. The ZCD
comparator looks for the zero crossing on the auxiliary winding
and switches when the auxiliary voltage is below zero.
Switching in the valley of the oscillation minimizes the
switching losses and reduces EMI noise.
The PFC controller uses a current sensor for overcurrent
protection. The boost inductor peak current is measured
across an external resistor in the switching circuit on a
cycle-by-cycle basis. An overcurrent fault is generated when
the sense voltage applied to the CS pin exceeds a predefined
reference voltage.
The CS1501 includes a supervisor and protection circuit to
manage startup, shutdown, and fault conditions. The
protection circuit is designed to prevent output overvoltage as
a result of load and AC mains transients. The PFC power
converter main rectified voltage (Vrect) and output link voltage
(Vlink) are monitored for overvoltage faults which would lead to
shutdown of the PFC controller. The PFC overvoltage
protection is designed for auto-recovery; operation resumes
once the fault clears.
2
DS927F4



Cirrus Logic CS1501
2. PIN DESCRIPTION
CS1501
Link V oltage S ens e
S tandby
Rec tifier V oltage S ens e
P FC Current S ens e
IFB
S TBY
IA C
CS
1
8
2
7
3
6
4
5
8-lead S OIC
VDD
GD
GND
ZC D
IC S upply V oltage
P FC Gate Driv er
Ground
P FC Zero-c urrent Detec t
Figure 2. CS1501 Pin Assignments
Pin Name
IFB
Pin #
1
STBY
2
IAC
3
CS
4
ZCD
5
GND
6
GD
7
VDD
8
I/O
IN
IN
IN
IN
IN
PWR
OUT
PWR
Description
Link Voltage Sense — A current proportional to the output link voltage of the PFC is
input here. The current is measured with an ADC.
Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state.
The input has an internal 600kpull-up resistor to the VDD pin.
Rectifier Voltage Sense — A current proportional to the rectified line voltage is input
here. The current is measured with an ADC.
PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a
resistor. The resulting voltage is applied to this pin and digitized for use by the PFC
computational logic to limit the maximum current through the power FET.
PFC Zero-current Detect — Boost Inductor demagnetization sensing input for
zero-current detection (ZCD) information. The pin is externally connected to the PFC
boost inductor auxiliary winding through an external resistor divider.
Ground — Common reference. Current return for both the input signal portion of the IC
and the gate driver.
PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a
peak current of 0.5A source and 1.0A sink.
IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the
gate driver. A storage capacitor is connected on this pin to serve as a reservoir for oper-
ating current for the device, including the gate drive current to the power transistor. This
pin is clamped to a maximum voltage (Vz) by an internal zener function.
DS927F4
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