unbuffered inverter. 74AUP1GU04GM Datasheet

74AUP1GU04GM inverter. Datasheet pdf. Equivalent

74AUP1GU04GM Datasheet
Recommendation 74AUP1GU04GM Datasheet
Part 74AUP1GU04GM
Description Low-power unbuffered inverter
Feature 74AUP1GU04GM; 74AUP1GU04 Low-power unbuffered inverter Rev. 5 — 29 June 2012 Product data sheet 1. General descr.
Manufacture nexperia
Datasheet
Download 74AUP1GU04GM Datasheet




nexperia 74AUP1GU04GM
74AUP1GU04
Low-power unbuffered inverter
Rev. 5 — 29 June 2012
Product data sheet
1. General description
The 74AUP1GU04 provides the single unbuffered inverting gate.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1GU04GW 40 C to +125 C TSSOP5
74AUP1GU04GM 40 C to +125 C XSON6
74AUP1GU04GF 40 C to +125 C XSON6
74AUP1GU04GN 40 C to +125 C XSON6
74AUP1GU04GS 40 C to +125 C XSON6
74AUP1GU04GX 40 C to +125 C X2SON5
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226



nexperia 74AUP1GU04GM
Nexperia
74AUP1GU04
Low-power unbuffered inverter
4. Marking
Table 2. Marking
Type number
74AUP1GU04GW
74AUP1GU04GM
74AUP1GU04GF
74AUP1GU04GN
74AUP1GU04GS
74AUP1GU04GX
Marking code[1]
pD
pD
pD
pD
pD
pD
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
2A
Y4
2
1
4
mna108
Fig 1. Logic symbol
mna109
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
540 Ω
A
VCC
50 Ω
Y
Fig 3. Logic diagram
001aad 073
74AUP1GU04
n.c. 1
A2
5 VCC
GND 3
4Y
001aaf167
Fig 4. Pin configuration SOT353-1
74AUP1GU04
n.c. 1
6 VCC
A2
5 n.c.
GND 3
4Y
001aaf168
Transparent top view
Fig 5. Pin configuration SOT886
74AUP1GU04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 June 2012
© Nexperia B.V. 2017. All rights reserved
2 of 21



nexperia 74AUP1GU04GM
Nexperia
74AUP1GU04
Low-power unbuffered inverter
74AUP1GU04
n.c. 1
A2
6 VCC
5 n.c.
GND 3
4Y
001aaf169
Transparent top view
Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202
6.2 Pin description
Table 3.
Symbol
n.c.
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5 and X2SON5 XSON6
1
1
2
2
3
3
4
4
-
5
5
6
7. Functional description
Table 4.
Input
A
L
H
Function table[1]
[1] H = HIGH voltage level; L = LOW voltage level.
74AUP1GU04
n.c. 1
3
GND
5 VCC
A2
4Y
aaa-003014
Transparent top view
Fig 7. Pin configuration SOT1226 (X2SON5)
Description
not connected
data input
ground (0 V)
data output
not connected
supply voltage
Output
Y
H
L
74AUP1GU04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 June 2012
© Nexperia B.V. 2017. All rights reserved
3 of 21







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