Dual 2-Bit Bistable Transparent Latch
Data sheet acquired from Harris Semiconductor SCHS135F
March 1998 - Revised October 2003
CD54HC75, CD74HC75, CD54HCT75,...
Description
Data sheet acquired from Harris Semiconductor SCHS135F
March 1998 - Revised October 2003
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75
Dual 2-Bit Bistable Transparent Latch
[ /Title (CD74 HC75, CD74 HCT75 ) /Subject (Dual 2-Bit Bistabl e
Features
Description
True and Complementary Outputs
Buffered Inputs and Outputs
Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected.
Ordering Information
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC75F3A
-55 to 125
16 Ld CERDIP
CD54HCT75F3A
-55 to 125
16 Ld CERDIP
CD74HC75E
-55 to 125
16 Ld PDIP
CD74HC75M
-55 to 125
16 Ld SOIC
CD74HC75MT
-55 to 125
16 Ld SOIC
CD74HC75M96
-55 to 125
16 Ld ...
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