Shift Register. CD54HCT166F3A Datasheet

CD54HCT166F3A Register. Datasheet pdf. Equivalent

CD54HCT166F3A Datasheet
Recommendation CD54HCT166F3A Datasheet
Part CD54HCT166F3A
Description 8-Bit Parallel-In/Serial-Out Shift Register
Feature CD54HCT166F3A; Data sheet acquired from Harris Semiconductor SCHS157C February 1998 - Revised October 2003 CD54HC1.
Manufacture etcTI
Datasheet
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Texas Instruments CD54HCT166F3A
Data sheet acquired from Harris Semiconductor
SCHS157C
February 1998 - Revised October 2003
CD54HC166, CD74HC166,
CD54HCT166, CD74HCT166
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
[ /Title
(CD74
HC166
,
CD74
HCT16
6)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Paral-
lel-
In/Seri
Features
Description
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
Pinout
CD54HC166, CD54HCT166
(CERDIP)
CD74HC166, CD74HCT166
(PDIP, SOIC)
TOP VIEW
DS 1
D0 2
D1 3
D2 4
D3 5
CE 6
CP 7
GND 8
16 VCC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
9 MR
The ’HC166 and ’HCT166 8-bit shift register is fabricated
with silicon gate CMOS technology. It possesses the low
power consumption of standard CMOS integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky device.
The ’HCT166 is functionally and pin compatible with the
standard ’LS166.
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW Parallel
Enable (PE) input. When the PE is LOW one setup time before
the LOW-to-HIGH clock transition, parallel data is entered into
the register. When PE is HIGH, data is entered into the internal
bit position Q0 from Serial Data Input (DS), and the remaining
bits are shifted one place to the right (Q0 Q1 Q2, etc.)
with each positive-going clock transition. For expansion of the
register in parallel to serial converters, the Q7 output is con-
nected to the DS input of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
can be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC166F3A
-55 to 125
16 Ld CERDIP
CD54HCT166F3A
-55 to 125
16 Ld CERDIP
CD74HC166E
-55 to 125
16 Ld PDIP
CD74HC166M
-55 to 125
16 Ld SOIC
CD74HC166MT
-55 to 125
16 Ld SOIC
CD74HC166M96
-55 to 125
16 Ld SOIC
CD74HCT166E
-55 to 125
16 Ld PDIP
CD74HCT166M
-55 to 125
16 Ld SOIC
CD74HCT166MT
-55 to 125
16 Ld SOIC
CD74HCT166M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



Texas Instruments CD54HCT166F3A
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
D0
D7
DS
8 - REGISTERS
Q7
CP
CE
MR
TRUTH TABLE
INPUTS
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE
CLOCK
SERIAL
PARALLEL
D0 D7
INTERNAL
Q STATES
Q0
Q1
OUTPUT
Q7
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
Q00
Q10
Q0
H
L
L
X
a...h
a
b
h
H
H
L
H
X
H
Q0n
Q6n
H
H
L
L
X
L
Q0n
Q6n
H
X
H
X
X
Q00
Q10
Q70
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
= Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent transition of the clock.
2



Texas Instruments CD54HCT166F3A
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH
-
-
VIL
-
-
VOH
VOL
II
VIH or
VIL
-0.02
-0.02
-0.02
-4
-5.2
VIH or
VIL
0.02
0.02
0.02
4
5.2
VCC or
-
GND
2
1.5 -
-
4.5 3.15 -
-
6
4.2 -
-
2
-
- 0.5
4.5
-
- 1.35
6
-
- 1.8
2
1.9 -
-
4.5 4.4 -
-
6
5.9 -
-
4.5 3.98 -
-
6
5.48 -
-
2
-
- 0.1
4.5
-
- 0.1
6
-
- 0.1
4.5
-
- 0.26
6
-
- 0.26
6
-
- ±0.1
-40oC TO 85oC
MIN MAX
1.5
-
3.15
-
4.2
-
-
0.5
-
1.35
-
1.8
1.9
-
4.4
-
5.9
-
3.84
-
5.34
-
-
0.1
-
0.1
-
0.1
-
0.33
-
0.33
-
±1
-55oC TO 125oC
MIN MAX UNITS
1.5
-
V
3.15
-
V
4.2
-
V
-
0.5
V
-
1.35
V
-
1.8
V
1.9
-
V
4.4
-
V
5.9
-
V
3.7
-
V
5.2
-
V
-
0.1
V
-
0.1
V
-
0.1
V
-
0.4
V
-
0.4
V
-
±1
µA
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