Ethernet Controller. AX88796C Datasheet

AX88796C Controller. Datasheet pdf. Equivalent

AX88796C Datasheet
Recommendation AX88796C Datasheet
Part AX88796C
Description Low-Power SPI or Non-PCI Ethernet Controller
Feature AX88796C; AX88796C Low-Power SPI or Non-PCI Ethernet Controller Features Document No.: AX88796C/V1.14/04/15/.
Manufacture ASIX
Datasheet
Download AX88796C Datasheet




ASIX AX88796C
AX88796C
Low-Power SPI or Non-PCI Ethernet Controller
Features
Document No.: AX88796C/V1.14/04/15/11
High-performance non-PCI local bus
Supports 8/16-bit SRAM-like host interface (US
Patent Approval), easily interfaced to most
common embedded MCUs; or 8/16-bit local CPU
interface including MCS-51 series, Renesas series
CPUs
Supports Slave-DMA to minimize CPU overhead
and burst mode read & write access for frame
reception & transmission on SRAM-like interface
for high performance applications
Supports variable voltage I/O (1.8/2.5/3.3V) and
programmable driving strength (8/16mA)
Interrupt pin with programmable timer
High-performance SPI slave interface
Supports SPI slave interface for CPU with SPI
master. The SPI slave interface supports SPI timing
mode 0 and 3, up to 40MHz of SPI CLK, variable
voltage I/O and programmable driving strength
Supports optional Ready signal as flow control for
SPI packet RX/TX
Single-chip Fast Ethernet MAC/PHY controller
Embeds 14KB SRAM for packet buffers
Supports IPv4/IPv6 packet Checksum Offload
Engine to reduce CPU loading, including IPv4
IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICM
Pv6 checksum generation & check
Supports VLAN match filter
Integrates IEEE 802.3/802.3u standards compatible
10BASE-T/100BASE-TX (twisted pair copper
mode) Fast Ethernet MAC/PHY transceiver in one
single-chip
Supports twisted pair crossover detection and
correction (HP Auto-MDIX)
Supports full duplex operation with IEEE 802.3x
flow control and half duplex operation with
back-pressure flow control
Supports auto-polling function
Supports 10/100Mbps N-way Auto-negotiation
operation
Advanced Power Management features
Supports dynamic power management to reduce
power dissipation during idle or light traffic period
Supports very low power Wake-On-LAN (WOL)
mode when the system enters sleep mode and waits
for network event to awake it up. The wakeup
events supported are network link state change,
receipt of a Magic Packet or a pre-programmed
Microsoft Wakeup Frame or through GPIO pin
Supports Protocol Offload (ARP & NS) for
Windows 7 Networking Power Management
Supports complete I/O pins isolation during WOL
mode or Remote Wakeup Ready mode to reduce
leakage current on non-PCI and SPI slave host
interface
Supports optional EEPROM interface to store MAC
address
Supports up to four GPIOs and two of them support
Wake-On-LAN
Supports programmable LED pins for various
network activity indications with variable voltage I/O
and programmable driving strength
Integrates voltage regulator, 25MHz crystal oscillator
and power on reset circuit on chip
Supports optional clock output (25, 50 or 100MHz)
for system use, if 25MHz crystal is present
Supports optional clock input (25MHz) from system
clock to save the 25MHz crystal cost
64-pin LQFP RoHS compliant package
Operates over 0 to +70°C or -40 to +85°C temperature
range
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
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ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Release Date: 04/15/2011
http://www.asix.com.tw



ASIX AX88796C
AX88796C
Low-Power SPI or Non-PCI Ethernet Controller
Target Applications
Netbook
Industrial Computer
Cable, Satellite and IP STB
IPTV, Digital Media Adapter
Network DVD, DVR-R, HDD
IP/Video Phone, VoIP ATA
Internet Radio
POS Terminal, Kiosk
Multi Functional Printer
RFID Reader
Time Attendance
RS232/422/485 to Ethernet
Building / Home Automation
HVAC Control
Networked Home Appliance
Security System
Biometric Access Control
Fingerprint Reader
Network Camera
Remote Surveillance
Professional DVR
Fire and Safety
Industrial Control
Remote Data Collection
Equipment
Remote Monitor
Remote Control and
Management
Environment Monitoring or
Network Sensor
Automatic Meter Reading
Networked UPS
Lighting Control
System Block Diagram
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ASIX ELECTRONICS CORPORATION



ASIX AX88796C
AX88796C
Low-Power SPI or Non-PCI Ethernet Controller
Table of Contents
1.0 Introduction......................................................................................................................... 10
1.1 General Description .......................................................................................................... 10
1.2 Block Diagram .................................................................................................................. 10
1.3 Pin Connection Diagram....................................................................................................11
1.3.1 8/16-Bit SRAM-like or Renesas SHx Series CPU Bus Mode .................................................................. 11
1.3.2 8/16-Bit Address-Data Multiplex or MCS-51 Bus Mode .........................................................................12
1.3.3 SPI Bus Mode...........................................................................................................................................13
1.4 Bus Interface Configuration Table and Application ......................................................... 14
1.4.1 8-Bit SRAM-like Bus Interface ................................................................................................................14
1.4.2 16-Bit SRAM-like Bus Interface ..............................................................................................................15
1.4.3 MCS-51 Bus Interface..............................................................................................................................15
1.4.4 8-Bit Address-Data Multiplex Bus Interface ............................................................................................16
1.4.5 16-Bit Address-Data Multiplex Bus Interface ..........................................................................................16
1.4.6 Renesas SHx series CPU Bus Interface....................................................................................................17
1.4.7 SPI Mode Bus Interface............................................................................................................................17
2.0 Signal Description ............................................................................................................... 18
2.1 Local CPU Bus Interface Signals Group .......................................................................... 18
2.2 10/100Mbps Twisted-Pair Interface Signals Group.......................................................... 20
2.3 Build-in PHY LED Indicator Signals Group .................................................................... 20
2.4 EEPROM Signals Group .................................................................................................. 21
2.5 SPI Interface Signals Group ............................................................................................. 22
2.6 Miscellaneous Signals Group ........................................................................................... 22
3.0 Memory Mapping Table ..................................................................................................... 24
3.1 EEPROM Memory Format Table ..................................................................................... 24
3.2 Internal Memory Mapping Table ...................................................................................... 27
3.2.1 Register Read/Write Access .....................................................................................................................28
3.2.2 RX/TX Packet Buffer Access ...................................................................................................................28
4.0 Basic Operation................................................................................................................... 29
4.1 Receiver Filtering ............................................................................................................. 29
4.1.1 Unicast Address Match Filter ...................................................................................................................29
4.1.2 Multicast Address Match Filter ................................................................................................................30
4.1.3 Broadcast Address Match Filter ...............................................................................................................32
4.1.4 VLAN Match Filter ..................................................................................................................................32
4.2 Buffer Management Operation ......................................................................................... 33
4.3 Packet Reception............................................................................................................... 33
4.4 Packet Transmission ......................................................................................................... 34
4.5 Filling Packet to Transmit Buffer: Host write data to TX memory .................................. 36
4.6 Removing Packets from the Ring: Host read data from RX memory .............................. 40
4.7 Wake-up Detection............................................................................................................ 44
4.7.1 Wake-up frame .........................................................................................................................................44
4.7.2 Magic Packet frame..................................................................................................................................46
4.7.3 Link Change Wakeup ...............................................................................................................................47
4.7.4 GPIO Wakeup...........................................................................................................................................47
4.8 Flow Control ..................................................................................................................... 48
4.8.1 Full-Duplex Flow Control ........................................................................................................................48
4.8.2 Half-Duplex Flow Control........................................................................................................................49
4.9 Auto-Polling Function ...................................................................................................... 49
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ASIX ELECTRONICS CORPORATION





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