Ethernet Controller. AX88796 Datasheet

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AX88796 Datasheet
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Part AX88796
Description 3-in-1 Local Bus Fast Ethernet Controller
Feature AX88796; AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet C.
Manufacture ASIX
Datasheet
Download AX88796 Datasheet




ASIX AX88796
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller
with Embedded SRAM
Document No.: AX796-17 / V1.7 / Jan. 25 ’02
Features
Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
Embedded 8K * 16 bit SRAM
Compliant with IEEE 802.3/802.3u
100BASE-TX/FX specification
NE2000 register level compatible instruction
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides an extra MII port for supporting other
media. For example, Home LAN application
Support EEPROM interface to store MAC address
External and internal loop-back capability
Support Standard Print Port for printer server
application
Support upto 3/1 General Purpose In/Out pins
128-pin LQFP low profile package
Low Power Consumption, typical under 100mA
0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are
the property of their respective holders.
Product description
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
System Block Diagram
AD BUS
Addr L
Addr H
Ctl BUS
AX88796
With
10/100 Mbps
PHY/TxRx
Optional Print Port
Or General I/O Ports
Optional
Home LAN
PHY
RJ11
RJ45
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : July/31/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw



ASIX AX88796
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 5
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5
1.2 AX88796 BLOCK DIAGRAM: .............................................................................................................................. 5
1.3A AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6
1.3B AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION ........................................................................ 7
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode................................................................................ 8
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode .............................................................................. 10
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11
2.0 SIGNAL DESCRIPTION ................................................................................................................................. 12
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 12
2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ......................................................................................... 13
2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..................................................................................................... 13
2.4 EEPROM SIGNALS GROUP .............................................................................................................................. 14
2.5 MII INTERFACE SIGNALS GROUP(OPTIONAL) ..................................................................................................... 14
2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL)................................................................ 15
2.7 GENERAL PURPOSE I/O PINS GROUP........................................................................................... 15
2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 16
2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE..................... 17
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 18
3.2 I/O MAPPING................................................................................................................................................... 18
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 18
4.0 BASIC OPERATION ...................................................................................................................................... 19
4.1 RECEIVER FILTERING ....................................................................................................................................... 19
4.1.1 Unicast Address Match Filter................................................................................................................... 19
4.1.2 Multicast Address Match Filter ................................................................................................................ 19
4.1.3 Broadcast Address Match Filter............................................................................................................... 20
4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20
4.2 BUFFER MANAGEMENT OPERATION .................................................................................................................. 22
4.2.1 Packet Reception ..................................................................................................................................... 22
4.2.2 Packet Transmision.................................................................................................................................. 25
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) .................................................................... 27
4.2.4 Removing Packets from the Ring (Host read data from memory) .............................................................. 28
4.2.5 Other Useful Operations .......................................................................................................................... 31
5.0 REGISTERS OPERATION ............................................................................................................................. 32
5.1 MAC CORE REGISTERS.................................................................................................................................... 32
5.1.1 Command Register (CR) Offset 00H (Read/Write) ................................................................................... 34
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 34
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 35
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35
5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36
5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 37
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 37
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37
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ASIX ELECTRONICS CORPORATION



ASIX AX88796
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
5.1.13 Test Register (TR) Offset 15H (Write).................................................................................................... 37
5.1.14 Test Register (TR) Offset 15H (Read) .................................................................................................... 38
5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)...................................................................... 38
5.1.16 GPO and Control (GPOC) Offset 17H (Write)....................................................................................... 38
5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) ............................................................... 39
5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read)........................................................................ 39
5.1.19 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)....................................................... 39
5.2 THE EMBEDDED PHY REGISTERS ..................................................................................................................... 40
5.2.1 MR0 -- Control Register Bit Descriptions................................................................................................. 41
5.2.2 MR1 -- Status Register Bit Descriptions ................................................................................................... 42
5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions.............................................................. 43
5.2.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions............................................................ 43
5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 43
5.2.6 MR5 –Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit Descriptions ............................. 44
5.2.7 MR6 – Autonegotiation Expansion Register Bit Descriptions ................................................................... 44
5.2.8 MR7 –Next Page Transmit Register Bit Descriptions ............................................................................... 45
5.2.9 MR16 – PCS Control Register Bit Descriptions........................................................................................ 45
5.2.10 MR17 –Autonegotiation Register A Bit Descriptions .............................................................................. 46
5.2.11 MR18 –Autonegotiation Register B Bit Descriptions .............................................................................. 46
5.2.12 MR20 –User Defined Register Bit Descriptions...................................................................................... 46
5.2.13 MR21 –RXER Counter Register Bit Descriptions ................................................................................... 47
5.2.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions..................................................... 47
5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions................................................. 48
5.2.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions................................................... 49
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions ........................................................ 50
6.0 CPU I/O READ AND WRITE FUNCTIONS ................................................................................................. 51
6.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 51
6.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 51
6.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 52
6.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .................................................................................................... 52
6.5 CPU ACCESS MII STATION MANAGEMENT FUNCTIONS. .................................................................................... 53
7.0 ELECTRICAL SPECIFICATION AND TIMINGS....................................................................................... 54
7.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 54
7.2 GENERAL OPERATION CONDITIONS................................................................................................................... 54
7.3 DC CHARACTERISTICS..................................................................................................................................... 54
7.4 A.C. TIMING CHARACTERISTICS....................................................................................................................... 55
7.4.1 XTAL / CLOCK........................................................................................................................................ 55
7.4.2 Reset Timing ............................................................................................................................................ 55
7.4.3 ISA Bus Access Timing............................................................................................................................. 57
7.4.4 80186 Type I/O Access Timing ................................................................................................................. 58
7.4.5 68K Type I/O Access Timing .................................................................................................................... 59
7.4.6 8051 Bus Access Timing........................................................................................................................... 60
7.4.7 MII Timing............................................................................................................................................... 61
8.0 PACKAGE INFORMATION........................................................................................................................... 62
APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 63
A.1 USING CRYSTAL 25MHZ ................................................................................................................ 63
A.2 USING OSCILLATOR 25MHZ......................................................................................................... 63
APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 64
ERRATA OF AX88796 .......................................................................................................................................... 65
DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY .............................. 66
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