AX11005

Features AX11001/AX11005 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Document No: AX1100x/V1.09/06/14/2011 MCU 8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100Mhz (100 MIPS) 100% software compatible with standard 8051/80390 2 GPIO ports of 8 bits each 2 external interrupt sources with 2 priority levels Support power management unit, programmable watchdog timer, and 3 16-bit timer/counters Debug port for connecting to In-Circuit Emulation (ICE) adaptor 5 channels of programmable counter array Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations Support twisted pair crossover detection and auto-correction (HP Auto-MDIX) Support wakeup via Link-up, Magic packet, Wakeup frame, external input pin or UART TCP/IP Build in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware Support TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software On-chip Program and Data Memory Embed 128K (AX11001) or 512KB (AX11005) Flash memory without bank select, and 16KB SRAM for program code mirroring Support initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP) Support reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent...