Signal MCU. MD6601 Datasheet

MD6601 MCU. Datasheet pdf. Equivalent

MD6601 Datasheet
Recommendation MD6601 Datasheet
Part MD6601
Description Mixed Signal MCU
Feature MD6601; Mixed Signal MCU MD6601 Data Sheet MD6601 Data Sheet Rev. 1.0 Date of issue 2014.03.06 Publicat.
Manufacture Sanken
Datasheet
Download MD6601 Datasheet





Sanken MD6601
Mixed Signal MCU
MD6601
Data Sheet
MD6601 Data Sheet
Rev. 1.0
Date of issue
2014.03.06
Publication
SANKEN ELECTRIC CO.,LTD.
Editing
SANKEN ELECTRIC CO.,LTD.
Copyright (C) 2014 SANKEN ELECTRIC CO.,LTD.
MD6601 - DS Rev.1.0
SANKEN ELECTRIC CO.,LTD.
1
Mar. 06, 2014
http://www.sanken-ele.co.jp/en/



Sanken MD6601
MD6601
CONTENTS
1. Product Overview ------------------------------------------------------------------------------------------------------ 1-1
1.1 Features --------------------------------------------------------------------------------------------------------- 1-1
1.1.1 Analog Sub System------------------------------------------------------------------------------------ 1-1
1.1.2 Digital Sub System ------------------------------------------------------------------------------------ 1-1
1.2 Description ----------------------------------------------------------------------------------------------------- 1-3
1.3 Application ----------------------------------------------------------------------------------------------------- 1-3
1.4 Ordering Information ----------------------------------------------------------------------------------------- 1-3
2. Block Diagram---------------------------------------------------------------------------------------------------------- 2-1
3. Pin Description --------------------------------------------------------------------------------------------------------- 3-1
3.1 Pin Arrangement ---------------------------------------------------------------------------------------------- 3-1
3.2 Signal Description -------------------------------------------------------------------------------------------- 3-2
4. Reset System and Low Voltage Detector (LVD) ----------------------------------------------------------------- 4-1
4.1 Overview ------------------------------------------------------------------------------------------------------- 4-1
4.2 Register Description ------------------------------------------------------------------------------------------ 4-2
4.2.1 Detect low power-supply voltage ------------------------------------------------------------------- 4-2
5. Clock System ----------------------------------------------------------------------------------------------------------- 5-1
5.1 Overview ------------------------------------------------------------------------------------------------------- 5-1
5.2 Register Description ------------------------------------------------------------------------------------------ 5-2
5.2.1 Clock controller ---------------------------------------------------------------------------------------- 5-2
5.2.2 Low Power Controller -------------------------------------------------------------------------------- 5-5
5.3 Clock Initialization Sequence ------------------------------------------------------------------------------- 5-5
5.4 Low Power Mode --------------------------------------------------------------------------------------------- 5-5
5.4.1 SLEEP Mode ------------------------------------------------------------------------------------------- 5-6
5.4.2 STBY Mode -------------------------------------------------------------------------------------------- 5-7
5.5 An example way to configure Clock Settings after Power On ---------------------------------------- 5-8
5.6 Limitation of Clock System --------------------------------------------------------------------------------- 5-9
5.6.1 Limitation of Low Power Mode --------------------------------------------------------------------- 5-9
6. 8051 CPU Subsystem-------------------------------------------------------------------------------------------------- 6-1
6.1 Introduction ---------------------------------------------------------------------------------------------------- 6-1
6.2 Overview ------------------------------------------------------------------------------------------------------- 6-1
6.3 System Configuration around CPU ------------------------------------------------------------------------ 6-2
6.4 Memory Map -------------------------------------------------------------------------------------------------- 6-3
6.5 Register Description ------------------------------------------------------------------------------------------ 6-5
6.5.1 Remap Control (REMAP) ---------------------------------------------------------------------------- 6-5
6.6 Instruction Code Map ---------------------------------------------------------------------------------------- 6-6
6.6.1 Notes on Instruction Spec ---------------------------------------------------------------------------- 6-7
6.6.2 CPU Instruction Execution Cycle ------------------------------------------------------------------- 6-8
7. Register Mapping------------------------------------------------------------------------------------------------------- 7-1
7.1 Peripherals on XDATA-Bus -------------------------------------------------------------------------------- 7-1
7.2 Peripherals on SFR-Bus-------------------------------------------------------------------------------------- 7-2
7.3 Scratch Pad Register ------------------------------------------------------------------------------------------ 7-3
8. GPIO 8-1
8.1 GPIO Structure ------------------------------------------------------------------------------------------------ 8-1
MD6601 - DS Rev.1.0
SANKEN ELECTRIC CO.,LTD.
C-1
Mar. 06, 2014



Sanken MD6601
MD6601
8.2 Register Description ------------------------------------------------------------------------------------------ 8-3
8.2.1 Pin Function Select for GPIO0 (PFS0)------------------------------------------------------------- 8-4
8.2.2 Pin Function Select for GPIOn (PFSn) (n=1-3) -------------------------------------------------- 8-4
8.2.3 Pin Data Direction for GPIOn (PDDn) (n=0-3) -------------------------------------------------- 8-5
8.2.4 Pin Data for GPIOn (PDRn) (n=0-3) --------------------------------------------------------------- 8-5
8.2.5 Pin Pull Up Control for GPIOn (PPUn) (n=0-3) ------------------------------------------------- 8-6
8.2.6 Pin Interrupt Enable for GPIOn (PIEn) (n=0-3) -------------------------------------------------- 8-6
8.2.7 Pin Interrupt Flag for GPIOn (PIFn) (n=0-3) ----------------------------------------------------- 8-7
8.2.8 Pin Interrupt Sense for GPIOn (PISn) (n=0-3)---------------------------------------------------- 8-7
8.2.9 Pin Interrupt Level for GPIOn (PILn) (n=0-3)---------------------------------------------------- 8-8
8.2.10 Pin Interrupt Both Edge for GPIOn (PIBn) (n=0-3) --------------------------------------------- 8-8
8.2.11 ADC Event Select from GPIOn (PEADCn) (n=0-3) -------------------------------------------- 8-9
8.2.12 PWM Event Select from GPIOn (PEPWMn) (n=0-3) ------------------------------------------ 8-9
8.2.13 PWM Event Gathering Method (PEMETHOD) ----------------------------------------------- 8-10
9. Event Connections in the LSI --------------------------------------------------------------------------------------- 9-1
10. Interrupt Controller -------------------------------------------------------------------------------------------------- 10-1
10.1 Overview ----------------------------------------------------------------------------------------------------- 10-1
10.2 Interrupt Vectors -------------------------------------------------------------------------------------------- 10-2
10.3 Register Description ---------------------------------------------------------------------------------------- 10-3
10.3.1 INTMST ---------------------------------------------------------------------------------------------- 10-3
10.3.2 INTENA ---------------------------------------------------------------------------------------------- 10-4
10.3.3 INTLVL ----------------------------------------------------------------------------------------------- 10-4
10.3.4 INTCFG----------------------------------------------------------------------------------------------- 10-5
10.3.5 INTFLG----------------------------------------------------------------------------------------------- 10-5
10.4 Operation ----------------------------------------------------------------------------------------------------- 10-6
10.4.1 Initial setting ----------------------------------------------------------------------------------------- 10-6
10.4.2 Interrupt flag ----------------------------------------------------------------------------------------- 10-6
10.4.3 Interrupt level ---------------------------------------------------------------------------------------- 10-6
10.4.4 Interrupt of external pins --------------------------------------------------------------------------- 10-8
11. DSAC (Direct SFR Access Controller)--------------------------------------------------------------------------- 11-1
11.1 Overview ----------------------------------------------------------------------------------------------------- 11-1
11.2 Event ---------------------------------------------------------------------------------------------------------- 11-2
11.3 Register Description ---------------------------------------------------------------------------------------- 11-3
11.3.1 DSACNTAn (DSAC Control A Register) ------------------------------------------------------- 11-4
11.3.2 DSACNTBn (DSAC Control B Register)------------------------------------------------------- 11-5
11.3.3 DSASRCn (DSAC Source address Register)--------------------------------------------------- 11-5
11.3.4 DSADSTn (DSAC Destination address Register) --------------------------------------------- 11-6
11.4 Operation ----------------------------------------------------------------------------------------------------- 11-6
11.5 Initialization sequence-------------------------------------------------------------------------------------- 11-8
11.6 Limitation of DSAC ---------------------------------------------------------------------------------------- 11-8
11.6.1 Disabling DSAC------------------------------------------------------------------------------------- 11-8
12. FLASH Memory Control ------------------------------------------------------------------------------------------- 12-1
12.1 Overview ----------------------------------------------------------------------------------------------------- 12-1
12.2 Flash memory mat structure ------------------------------------------------------------------------------- 12-3
12.3 Register Description ---------------------------------------------------------------------------------------- 12-4
12.3.1 FMTIME---------------------------------------------------------------------------------------------- 12-4
MD6601 - DS Rev.1.0
SANKEN ELECTRIC CO.,LTD.
C-2
Mar. 06, 2014





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)