Signal MCU. MD6603 Datasheet

MD6603 MCU. Datasheet pdf. Equivalent

MD6603 Datasheet
Recommendation MD6603 Datasheet
Part MD6603
Description Mixed Signal MCU
Feature MD6603; Mixed Signal MCU MD6603 Data Sheet MD6603-DSE Rev.1.1 SANKEN ELECTRIC CO., LTD. Apr. 06, 2018 h.
Manufacture Sanken
Datasheet
Download MD6603 Datasheet




Sanken MD6603
Mixed Signal MCU
MD6603
Data Sheet
MD6603-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
Apr. 06, 2018
http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2018



Sanken MD6603
MD6603
Contents
Contents ----------------------------------------------------------------------------------------------------------------------------------------------------- C-1
1. Product Overview -----------------------------------------------------------------------------------------------------------------------------------1-1
2. Block Diagram ---------------------------------------------------------------------------------------------------------------------------------------2-1
3. Pin Configuration Definitions --------------------------------------------------------------------------------------------------------------------3-1
3.1. Pin Configuration-----------------------------------------------------------------------------------------------------------------------------3-1
3.2. Pin Definitions (QFN40)---------------------------------------------------------------------------------------------------------------------3-2
4. System Controller (SYSC) ------------------------------------------------------------------------------------------------------------------------4-1
4.1. Overview ----------------------------------------------------------------------------------------------------------------------------------------4-1
4.2. Clock System -----------------------------------------------------------------------------------------------------------------------------------4-2
4.2.1. Clock Sources-----------------------------------------------------------------------------------------------------------------------------4-2
4.2.2. PLL Clock ---------------------------------------------------------------------------------------------------------------------------------4-3
4.2.3. Distribution Clocks ---------------------------------------------------------------------------------------------------------------------4-3
4.2.4. Module Clocks----------------------------------------------------------------------------------------------------------------------------4-4
4.2.5. Clock Setting Procedure ---------------------------------------------------------------------------------------------------------------4-5
4.3. Low Power Consumption Modes ---------------------------------------------------------------------------------------------------------4-6
4.3.1. Sleep Mode --------------------------------------------------------------------------------------------------------------------------------4-6
4.3.2. Standby Mode ----------------------------------------------------------------------------------------------------------------------------4-7
4.3.3. Inserting NOP Instruction at Transition to Sleep and Standby Modes----------------------------------------------------4-8
4.4. Reset Circuit -----------------------------------------------------------------------------------------------------------------------------------4-9
4.5. Low Voltage Detection (LVD) ----------------------------------------------------------------------------------------------------------- 4-10
4.6. Analog Infrastructure Control ---------------------------------------------------------------------------------------------------------- 4-11
4.7. Register Descriptions ---------------------------------------------------------------------------------------------------------------------- 4-12
4.7.1. CLKCFG0 (Clock Configuration0 Register) ----------------------------------------------------------------------------------- 4-13
4.7.2. CLKCFG1 (Clock Configuration1 Register) ----------------------------------------------------------------------------------- 4-14
4.7.3. PLLCFG (PLL Configuration Register) ---------------------------------------------------------------------------------------- 4-15
4.7.4. MCLKE0 (Module Clock Enable0 Register) ----------------------------------------------------------------------------------- 4-15
4.7.5. MCLKE1 (Module Clock Enable1 Register) ----------------------------------------------------------------------------------- 4-16
4.7.6. MCLKE2 (Module Clock Enable2 Register) ----------------------------------------------------------------------------------- 4-16
4.7.7. MCLKE3 (Module Clock Enable3 Register) ----------------------------------------------------------------------------------- 4-17
4.7.8. MCLKE4 (Module Clock Enable4 Register) ----------------------------------------------------------------------------------- 4-17
4.7.9. MCLKE5 (Module Clock Enable5 Register) ----------------------------------------------------------------------------------- 4-18
4.7.10. MCLKE6 (Module Clock Enable6 Register)---------------------------------------------------------------------------------- 4-18
4.7.11. PWMENBL (PWM Clock Enable Control Register) ----------------------------------------------------------------------- 4-19
4.7.12. PWMCSC0 (PWM Clock Source Control0 Register) ---------------------------------------------------------------------- 4-19
4.7.13. LVDCTRL (Low Voltage Detector Control Register) ---------------------------------------------------------------------- 4-20
4.7.14. REFCTRL (Reference Control Register) -------------------------------------------------------------------------------------- 4-21
4.7.15. RESCTRL (Resistor Control Register)----------------------------------------------------------------------------------------- 4-21
4.7.16. LPCTRL (Low Power Control Register)--------------------------------------------------------------------------------------- 4-22
4.7.17. CSBYCR (CMP Standby Control Register)----------------------------------------------------------------------------------- 4-23
4.7.18. DEVER (Device Version and Revision Register)----------------------------------------------------------------------------- 4-23
4.7.19. REMAP (Remap Control Register) --------------------------------------------------------------------------------------------- 4-24
4.7.20. BUSBUFCR (BUS Buffer Control Register) ---------------------------------------------------------------------------------- 4-24
4.7.21. LINECTRL (DBG Line Control Register) ------------------------------------------------------------------------------------ 4-25
4.7.22. TMR2INCR (TMR2 Input Control Register) -------------------------------------------------------------------------------- 4-25
4.8. Usage Notes and Restrictions ------------------------------------------------------------------------------------------------------------ 4-26
5. 8051 CPU ----------------------------------------------------------------------------------------------------------------------------------------------5-1
5.1. Overview ----------------------------------------------------------------------------------------------------------------------------------------5-1
5.2. CPU Peripheral System Configurations ------------------------------------------------------------------------------------------------5-2
5.3. Memory Map ----------------------------------------------------------------------------------------------------------------------------------5-3
5.4. Instruction Code Map -----------------------------------------------------------------------------------------------------------------------5-5
5.4.1. Notes on CPU Instruction -------------------------------------------------------------------------------------------------------------5-5
5.4.2. Execution Cycle Counts per Instruction-------------------------------------------------------------------------------------------5-6
5.5. Bus Configurations ---------------------------------------------------------------------------------------------------------------------------5-7
5.6. Bus Operational Descriptions--------------------------------------------------------------------------------------------------------------5-8
5.6.1. System Bus --------------------------------------------------------------------------------------------------------------------------------5-8
5.6.2. Bus Master --------------------------------------------------------------------------------------------------------------------------------5-9
5.6.3. Arbitration Circuit -------------------------------------------------------------------------------------------------------------------- 5-10
5.6.4. 16-bit Access Buffer------------------------------------------------------------------------------------------------------------------- 5-11
5.7. Usage Notes and Restrictions ------------------------------------------------------------------------------------------------------------ 5-12
MD6603-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
C-1
Apr. 06, 2018
http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2018



Sanken MD6603
MD6603
5.7.1.
5.7.2.
5.7.3.
5.7.4.
5.7.5.
5.7.6.
Restrictions on XDATA BUS Buffer --------------------------------------------------------------------------------------------- 5-12
Conflict between 16-bit Register Write and Interrupt ----------------------------------------------------------------------- 5-12
Access to RAM1 Area ---------------------------------------------------------------------------------------------------------------- 5-12
Access to XDATA Space ------------------------------------------------------------------------------------------------------------- 5-12
MOVX Instructions to Peripheral Registers of XDATA Space ----------------------------------------------------------- 5-12
EPU Operation While CPU Is Accessing UART Register ------------------------------------------------------------------ 5-12
6. Register Mapping------------------------------------------------------------------------------------------------------------------------------------6-1
6.1. Peripheral Address on XDATA BUS ----------------------------------------------------------------------------------------------------6-1
6.2. Peripheral Address on SFR BUS ---------------------------------------------------------------------------------------------------------6-3
6.3. SPRn (Scratch Pad Register n) (n = 0 to 7)---------------------------------------------------------------------------------------------6-5
7. GPIO----------------------------------------------------------------------------------------------------------------------------------------------------7-1
7.1. GPIO Structure -------------------------------------------------------------------------------------------------------------------------------7-1
7.2. Register Descriptions ------------------------------------------------------------------------------------------------------------------------7-3
7.2.1. PFS0 (Pin Function Select for GPIO0)---------------------------------------------------------------------------------------------7-5
7.2.2. PFSH0 (Pin Function Select High for GPIO0) -----------------------------------------------------------------------------------7-5
7.2.3. PFS1 (Pin Function Select for GPIO1)---------------------------------------------------------------------------------------------7-6
7.2.4. PFSE1 (Pin Function Extend Select for GPIO1) --------------------------------------------------------------------------------7-7
7.2.5. PFS2 (Pin Function Select for GPIO2)---------------------------------------------------------------------------------------------7-7
7.2.6. PFSE2 (Pin Function Extend Select for GPIO2) --------------------------------------------------------------------------------7-8
7.2.7. PDD0 (Pin Data Direction for GPIO0)---------------------------------------------------------------------------------------------7-8
7.2.8. PDD1 (Pin Data Direction for GPIO1)---------------------------------------------------------------------------------------------7-9
7.2.9. PDD2 (Pin Data Direction for GPIO2)---------------------------------------------------------------------------------------------7-9
7.2.10. PDR0 (Pin Data for GPIO0)------------------------------------------------------------------------------------------------------- 7-10
7.2.11. PDR1 (Pin Data for GPIO1)------------------------------------------------------------------------------------------------------- 7-11
7.2.12. PDR2 (Pin Data for GPIO2)------------------------------------------------------------------------------------------------------- 7-12
7.2.13. PPU0 (Pin Pull Up Control for GPIO0) ---------------------------------------------------------------------------------------- 7-13
7.2.14. PPU2 (Pin Pull Up Control for GPIO2) ---------------------------------------------------------------------------------------- 7-13
7.2.15. PPD1 (Pin Pull Down Control for GPIO1) ------------------------------------------------------------------------------------ 7-13
7.2.16. PIE0 (Pin Interrupt Enable for GPIO0) --------------------------------------------------------------------------------------- 7-14
7.2.17. PIE1 (Pin Interrupt Enable for GPIO1) --------------------------------------------------------------------------------------- 7-14
7.2.18. PIE2 (Pin Interrupt Enable for GPIO2) --------------------------------------------------------------------------------------- 7-15
7.2.19. PIF0 (Pin Interrupt Flag for GPIO0) ------------------------------------------------------------------------------------------- 7-15
7.2.20. PIF1 (Pin Interrupt Flag for GPIO1) ------------------------------------------------------------------------------------------- 7-16
7.2.21. PIF2 (Pin Interrupt Flag for GPIO2) ------------------------------------------------------------------------------------------- 7-16
7.2.22. PIS0 (Pin Interrupt Sense for GPIO0) ------------------------------------------------------------------------------------------ 7-17
7.2.23. PIS1 (Pin Interrupt Sense for GPIO1) ------------------------------------------------------------------------------------------ 7-17
7.2.24. PIS2 (Pin Interrupt Sense for GPIO2) ------------------------------------------------------------------------------------------ 7-18
7.2.25. PIL0 (Pin Interrupt Level for GPIO0)------------------------------------------------------------------------------------------ 7-18
7.2.26. PIL1 (Pin Interrupt Level for GPIO1)------------------------------------------------------------------------------------------ 7-19
7.2.27. PIL2 (Pin Interrupt Level for GPIO2)------------------------------------------------------------------------------------------ 7-19
7.2.28. PIB0 (Pin Interrupt Both Edge for GPIO0) ----------------------------------------------------------------------------------- 7-20
7.2.29. PIB1 (Pin Interrupt Both Edge for GPIO1) ----------------------------------------------------------------------------------- 7-20
7.2.30. PIB2 (Pin Interrupt Both Edge for GPIO2) ----------------------------------------------------------------------------------- 7-21
7.2.31. PEADC0 (ADC Event Select from GPIO0) ----------------------------------------------------------------------------------- 7-21
7.2.32. PEADC1 (ADC Event Select from GPIO1) ----------------------------------------------------------------------------------- 7-22
7.2.33. PEADC2 (ADC Event Select from GPIO2) ----------------------------------------------------------------------------------- 7-22
7.2.34. PEPWM0 (PWM Event Select from GPIO0) --------------------------------------------------------------------------------- 7-23
7.2.35. PEPWM1 (PWM Event Select from GPIO1) --------------------------------------------------------------------------------- 7-23
7.2.36. EPWM2 (PWM Event Select from GPIO2) ----------------------------------------------------------------------------------- 7-24
7.2.37. PELUT0 (LUT Event Select from GPIO0) ------------------------------------------------------------------------------------ 7-24
7.2.38. PELUT1 (LUT Event Select from GPIO1) ------------------------------------------------------------------------------------ 7-25
7.2.39. PELUT2 (LUT Event Select from GPIO2) ------------------------------------------------------------------------------------ 7-25
7.2.40. PEMETHOD (PWM and ADC Event Gathering Method)---------------------------------------------------------------- 7-26
7.2.41. LEMETHOD (CMPLUT Event Gathering Method) ----------------------------------------------------------------------- 7-26
7.2.42. SIS (Serial Input Select) ------------------------------------------------------------------------------------------------------------ 7-27
7.2.43. I2CIS (I2C Input Select) ------------------------------------------------------------------------------------------------------------ 7-27
7.2.44. TMRIS (TMR Input/Output Select)--------------------------------------------------------------------------------------------- 7-28
7.2.45. CLKIS (Clock Input Select) ------------------------------------------------------------------------------------------------------- 7-28
7.3. Usage Notes and Restrictions ------------------------------------------------------------------------------------------------------------ 7-29
7.3.1. Reading from PDRx Register after Writing to PDRx Register ------------------------------------------------------------ 7-29
7.3.2. Setting the Pin Functions: GPIO14, GPIO15, GPIO16, GPIO17, and GPIO21--------------------------------------- 7-29
8. Event Connection------------------------------------------------------------------------------------------------------------------------------------8-1
MD6603-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
C-2
Apr. 06, 2018
http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2018





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