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Termination Regulator. LP2996M Datasheet

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Termination Regulator. LP2996M Datasheet






LP2996M Regulator. Datasheet pdf. Equivalent




LP2996M Regulator. Datasheet pdf. Equivalent





Part

LP2996M

Description

Termination Regulator



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design LP2996-N, LP2996A SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016 LP2996-N, LP2996A DDR Termination Regulator 1 Features •1 Minimum VDDQ: – 1.8 V (LP2996-N) – 1.35 V (LP2996A) • Source and Si nk Current • Low Output Voltage Offse t • No External Resistors Requir.
Manufacture

Texas Instruments

Datasheet
Download LP2996M Datasheet


Texas Instruments LP2996M

LP2996M; ed for Setting Output Voltage • Linear Topology • Suspend to Ram (STR) Func tionality • Stable With Ceramic Capac itors With Appropriate ESR • Low Exte rnal Component Count • Thermal Shutdo wn 2 Applications • LP2996-N: DDR1 an d DDR2 Termination Voltage • LP2996A: DDR1, DDR2, DDR3, and DDR3L Terminatio n Voltage • FPGA • Industrial and M edical PC • SSTL-2 and SSTL-3 Termin.


Texas Instruments LP2996M

ation • HSTL Termination 3 Description The LP2996-N and LP2996A linear regula tors are designed to meet the JEDEC SST L-2 specifications for termination of D DR-SDRAM. The device also supports DDR2 , while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-s peed operational amplifier to provide e xcellent response to.


Texas Instruments LP2996M

load transients. The output stage preve nts shoot through while delivering 1.5- A continuous current and transient peak s up to 3 A in the application as requi red for DDR-SDRAM termination. The LP29 96-N and LP2996A also incorporate a VSE NSE pin to provide superior load regula tion and a VREF output as a reference f or the chipset and DIMMs. An additiona l feature found on.

Part

LP2996M

Description

Termination Regulator



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design LP2996-N, LP2996A SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016 LP2996-N, LP2996A DDR Termination Regulator 1 Features •1 Minimum VDDQ: – 1.8 V (LP2996-N) – 1.35 V (LP2996A) • Source and Si nk Current • Low Output Voltage Offse t • No External Resistors Requir.
Manufacture

Texas Instruments

Datasheet
Download LP2996M Datasheet




 LP2996M
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
LP2996-N, LP2996A
SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016
LP2996-N, LP2996A DDR Termination Regulator
1 Features
1 Minimum VDDQ:
– 1.8 V (LP2996-N)
– 1.35 V (LP2996A)
• Source and Sink Current
• Low Output Voltage Offset
• No External Resistors Required for Setting Output
Voltage
• Linear Topology
• Suspend to Ram (STR) Functionality
• Stable With Ceramic Capacitors With Appropriate
ESR
• Low External Component Count
• Thermal Shutdown
2 Applications
• LP2996-N: DDR1 and DDR2 Termination Voltage
• LP2996A: DDR1, DDR2, DDR3, and DDR3L
Termination Voltage
• FPGA
• Industrial and Medical PC
• SSTL-2 and SSTL-3 Termination
• HSTL Termination
3 Description
The LP2996-N and LP2996A linear regulators are
designed to meet the JEDEC SSTL-2 specifications
for termination of DDR-SDRAM. The device also
supports DDR2, while LP2996A supports DDR3 and
DDR3L VTT bus termination with VDDQ minimum of
1.35 V. The device contains a high-speed operational
amplifier to provide excellent response to load
transients. The output stage prevents shoot through
while delivering 1.5-A continuous current and
transient peaks up to 3 A in the application as
required for DDR-SDRAM termination. The LP2996-N
and LP2996A also incorporate a VSENSE pin to
provide superior load regulation and a VREF output
as a reference for the chipset and DIMMs.
An additional feature found on the LP2996-N and
LP2996A is an active-low shutdown (SD) pin that
provides Suspend To RAM (STR) functionality. When
SD is pulled low the VTT output will tri-state providing
a high impedance output, but VREF remains active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
TI recommends the LP2998 and LP2998-Q1 devices
for automotive applications and DDR applications that
require operating at temperatures below zero.
WEBENCH® design tools can be used by application
designers to generate, optimize, and simlulate
applications using the LP2998 and LP2998-Q1.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LP2996-N
SOIC (8)
4.90 mm x 3.90 mm
LP2996-N, LP2996A WSON (8)
4.90 mm x 3.90 mm
LP2996-N
WQFN (16)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
LP2996A
SD
VDDQ = 1.5 V
SD
VDDQ
VREF
VREF = 0.75 V
+
0.01PF
VDD = 2.5 V
AVIN
VSENSE
+
47 PF
PVIN
VTT
GND
VTT = 0.75 V
36
220 PF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 LP2996M
LP2996-N, LP2996A
SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ...................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8 Applications and Implementation ...................... 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
10.3 Thermal Considerations ........................................ 20
11 Device and Documentation Support ................. 23
11.1 Documentation Support ........................................ 23
11.2 Related Links ........................................................ 23
11.3 Receiving Notification of Documentation Updates 23
11.4 Community Resources.......................................... 23
11.5 Trademarks ........................................................... 23
11.6 Electrostatic Discharge Caution ............................ 23
11.7 Glossary ................................................................ 23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2013) to Revision K
Page
• Added Device Information table, Specifications section, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
• Added LP2996A throughout data sheet ................................................................................................................................. 1
• Added DDR3 support throughout data sheet ......................................................................................................................... 1
• Deleted Lead temperature (260°C maximum) from Absolute Maximum Ratings .................................................................. 5
• Changed Thermal Resistance, RθJA, values in Thermal Information From: 151°C/W To: 119.5°C/W (SOIC), From:
151°C/W To: 56.5°C/W (SO), and From: 151°C/W To: 52.7°C/W (WQFN)........................................................................... 5
Changes from Revision I (March 2013) to Revision J
Page
• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
• Added VDDQ Range ................................................................................................................................................................. 1
2
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Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: LP2996-N LP2996A




 LP2996M
www.ti.com
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
LP2996-N, LP2996A
SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016
DDA Package
8-Pin SO With PowerPAD
Top View
GND
1
8
SD
2
7
VSENSE
3
6
VREF
4
5
Not to scale
VTT
PVIN
AVIN
VDDQ
GND
SD
VSENSE
VREF
1
8
2
7
PowerPAD
3
6
4
5
NHP Package
16-Pin WQFN
Top View
Not to scale
VTT
PVIN
AVIN
VDDQ
NC
GND
NC
SD
1
12
2
11
Thermal Pad
3
10
4
9
PVIN
PVIN
AVIN
NC
Not to scale
NAME
AVIN
GND
PVIN
PIN
SO
PowerPAD
SOIC
6
6
1
1
7
7
WQFN
10
2
11, 12
Pin Functions
I/O
DESCRIPTION
Analog input pin. AVIN is used to supply all the internal control circuitry. This pin has the capability
to work from a supply separate from PVIN depending on the application. For SSTL-2 applications, a
I good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
voltage selection is that PVIN must be equal to or lower than AVIN.
— Ground
Power input pin. PVIN is used exclusively to provide the rail voltage for the output stage used to
create VTT. This pin has the capability to work from a supply separate from PVIN depending on the
application. Higher voltages on PVIN increases the maximum continuous output current because of
output RDS(ON) limitations at voltages close to VTT. The disadvantage of high values of PVIN is that
the internal power loss also increases, thermally limiting the design. For SSTL-2 applications, a
I
good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
voltage selection is that PVIN must be equal to or lower than AVIN. TI recommends connecting PVIN
to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of
excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown then
the part enters a shutdown state identical to the manual shutdown where VTT is tri-stated and
VREF remains active.
Copyright © 2002–2016, Texas Instruments Incorporated
Product Folder Links: LP2996-N LP2996A
Submit Documentation Feedback
3






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