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Communications Element. TL16C550C Datasheet

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Communications Element. TL16C550C Datasheet






TL16C550C Element. Datasheet pdf. Equivalent




TL16C550C Element. Datasheet pdf. Equivalent





Part

TL16C550C

Description

Asynchronous Communications Element



Feature


TL16C550C SLLS177I – MARCH 1994 – RE VISED MARCH 2021 TL16C550C Asynchronous Communications Element with Autoflow C ontrol 1 Features • Programmable Aut o-RTS and Auto-CTS • In Auto-CTSMode, CTS Controls Transmitter • In Auto-R TS Mode, RCV FIFO Contents and Threshol d Control RTS • Serial and Modem Cont rol Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same.
Manufacture

Texas Instruments

Datasheet
Download TL16C550C Datasheet


Texas Instruments TL16C550C

TL16C550C; Power Drop • Capable of Running With All Existing TL16C450 Software • Afte r Reset, All Registers Are Identical to the TL16C450 Register Set • Up to 16 -MHz Clock Rate for up to 1-Mbaud Opera tion • In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CP U and Serial Data • Programmable Baud Rate Generator Allows Divis.


Texas Instruments TL16C550C

ion of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 1 6×Clock • Standard Asynchronous Comm unication Bits (Start, Stop, and Parity ) Added to or Deleted From the Serial D ata Stream • 5-V and 3.3-V Operation • Independent Receiver Clock Input Transmit, Receive, Line Status, and D ata Set Interrupts Independently Contro lled • Fully Programmable Ser.


Texas Instruments TL16C550C

ial Interface Characteristics: – 5-, 6 -, 7-, or 8-Bit Characters – Even-, O dd-, or No-Parity Bit Generation and De tection – 1-, 1 1/2-, or 2-Stop Bit G eneration – Baud Generation (dc to 1 Mbit/s) • False-Start Bit Detection Complete Status Reporting Capabiliti es • 3-State Output TTL Drive Capabil ities for Bidirectional Data Bus and Co ntrol Bus • Line Break Generatio.

Part

TL16C550C

Description

Asynchronous Communications Element



Feature


TL16C550C SLLS177I – MARCH 1994 – RE VISED MARCH 2021 TL16C550C Asynchronous Communications Element with Autoflow C ontrol 1 Features • Programmable Aut o-RTS and Auto-CTS • In Auto-CTSMode, CTS Controls Transmitter • In Auto-R TS Mode, RCV FIFO Contents and Threshol d Control RTS • Serial and Modem Cont rol Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same.
Manufacture

Texas Instruments

Datasheet
Download TL16C550C Datasheet




 TL16C550C
TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021
TL16C550C Asynchronous Communications Element with Autoflow Control
1 Features
• Programmable Auto-RTS and Auto-CTS
• In Auto-CTSMode, CTS Controls Transmitter
• In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
• Serial and Modem Control Outputs Drive a RJ11
Cable Directly When Equipment Is on the Same
Power Drop
• Capable of Running With All Existing TL16C450
Software
• After Reset, All Registers Are Identical to the
TL16C450 Register Set
• Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
• In the TL16C450 Mode, Hold and Shift Registers
Eliminate the Need for Precise Synchronization
Between the CPU and Serial Data
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to (216
−1) and Generates an Internal 16×Clock
• Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted From
the Serial Data Stream
• 5-V and 3.3-V Operation
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
• Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation and
Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)
• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
– Loopback Controls for Communications Link
Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR, DTR,
RI, and DCD)
2 Description
The TL16C550C and the TL16C550CI are
functional upgrades of the TL16C550B asynchronous
communications element (ACE), which in turn is a
functional upgrade of the TL16C450. Functionally
equivalent to the TL16C450 on power up (character
or TL16C450 mode), the TL16C550C and the
TL16C550CI, like the TL16C550B, can be placed
in an alternate FIFO mode. This relieves the
CPU of excessive software overhead by buffering
received and transmitted characters. The receiver
and transmitter FIFOs store up to 16 bytes including
three additional bits of error status per byte for the
receiver FIFO. In the FIFO mode, there is a selectable
autoflow control feature that can significantly reduce
software overload and increase system efficiency by
automatically controlling serial data flow using RTS
output and CTS input signals.
The TL16C550C and TL16C550CI perform serial-
to-parallel conversions on data received from a
peripheral device or modem and parallel-to-serial
conversion on data received from its CPU. The
CPU can read the ACE status at any time. The
ACE includes complete modem control capability
and a processor interrupt system that can be
tailored to minimize software management of the
communications link.
Both the TL16C550C and the TL16C550CI ACE
include a programmable baud rate generator capable
of dividing a reference clock by divisors from 1 to
65535 and producing a 16× reference clock for the
internal transmitter logic. Provisions are included to
use this 16× clock for the receiver logic. The ACE
accommodates a 1-Mbaud serial rate (16-MHz input
clock) so that a bit time is 1 μs and a typical character
time is 10 μs (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions on the
TL16C550C and the TL16C550CI have been changed
to TXRDY and RXRDY, which provide signaling to a
DMA controller.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 TL16C550C
TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 6
5.1 Absolute Maximum Ratings........................................ 6
5.2 Recommended Operating Conditions (Low
Voltage - 3.3 nominal)................................................... 6
5.3 Recommended Operating Conditions (Standard
Voltage - 5 V nominal)................................................... 7
5.4 Thermal Information....................................................7
5.5 Electrical Characteristics (Low Voltage - 3.3 V
nominal).........................................................................8
5.6 Electrical Characteristics (Standard Voltage - 5
V nominal)..................................................................... 8
5.7 System Timing Requirements..................................... 9
5.8 System Switching Characteristics.............................10
5.9 Baud Generator Switching Characteristics............... 10
5.10 Receiver Switching Characteristics.........................10
5.11 Transmitter Switching Characteristics..................... 11
5.12 Modem Control Switching Characteristics.............. 11
6 Parameter Measurement Information.......................... 12
7 Detailed Description......................................................19
7.1 Autoflow Control (see Figure 7-1) ............................ 19
7.2 Auto-RTS (see Figure 7-1) .......................................19
7.3 Auto-CTS (see Figure 7-1) .......................................19
7.4 Enabling Autoflow Control and Auto-CTS ................19
7.5 Auto-CTS and Auto-RTS Functional Timing............. 20
7.6 Functional Block Diagram......................................... 21
7.7 Principles of Operation..............................................21
8 Application Information................................................ 33
9 Device and Documentation Support............................35
9.1 Receiving Notification of Documentation Updates....35
9.2 Support Resources................................................... 35
9.4 Electrostatic Discharge Caution................................35
9.5 Glossary....................................................................35
10 Mechanical, Packaging, and Orderable
Information.................................................................... 36
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2006) to Revision I (March 2021)
Page
• Updated the data sheet format........................................................................................................................... 1
• Added the Pin Configuration and Functions section...........................................................................................3
• Added the Thermal Information table. ............................................................................................................... 7
2
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 TL16C550C
www.ti.com
4 Pin Configuration and Functions
TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021
Figure 4-1. N Package (Top View)
Figure 4-2. FN Package (Top View)
Figure 4-3. PT/PFB Package (Top View)
NC - No internal connection
NAME
A0
A1
A2
ADS
TERMINAL
NO.N(1) NO.FN
28
31
27
30
26
29
25
28
NO.PT
28
27
26
24
Table 4-1. Pin Functions
I/O
DESCRIPTION
I
Register select. A0 −A2 are used during read and write operations to select the
ACE register to read from or write to. Refer to Table 1 for register addresses
and refer to ADS description.
I
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1,
and CS2 drive the internal select logic directly; when ADS is high, the register
select and chip select signals are held at the logic levels they were in when the
low-to-high transition of ADS occurred
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TL16C550C
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