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ACE. TL16C550BI Datasheet

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ACE. TL16C550BI Datasheet






TL16C550BI ACE. Datasheet pdf. Equivalent




TL16C550BI ACE. Datasheet pdf. Equivalent





Part

TL16C550BI

Description

ACE



Feature


TL16C550B, TL16C550BI ASYNCHRONOUS COMMU NICATIONS ELEMENT D Capable of Running With All Existing TL16C450 Software D After Reset, All Registers Are Identica l to the TL16C450 Register Set D In the FIFO Mode, Transmitter and Receiver Ar e Each Buffered With 16-Byte FIFOs to R educe the Number of Interrupts to the C PU D In the TL16C450 Mode, Hold and Shi ft Registers Elimi.
Manufacture

Texas Instruments

Datasheet
Download TL16C550BI Datasheet


Texas Instruments TL16C550BI

TL16C550BI; nate the Need for Precise Synchronizatio n Between the CPU and Serial Data D Pro grammable Baud Rate Generator Allows Di vision of Any Input Reference Clock by 1 to (216 – 1) and Generates an Inter nal 16× Clock D Standard Asynchronous Communication Bits (Start, Stop, and Pa rity) Added to or Deleted From the Seri al Data Stream D Independent Receiver C lock Input D Transmit.


Texas Instruments TL16C550BI

, Receive, Line Status, and Data Set Int errupts Independently Controlled SLLS1 36B – JANUARY 1994 – REVISED AUGUST 1996 D Fully Programmable Serial Inter face Characteristics: – 5-, 6-, 7-, o r 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generatio n – Baud Generation (DC to 562 Kbit/s ) D False-Start Bit Detection .


Texas Instruments TL16C550BI

D Complete Status Reporting Capabilities D 3-State Outputs Provide TTL Drive Ca pabilities for Bidirectional Data Bus a nd Control Bus D Line Break Generation and Detection D Internal Diagnostic Cap abilities: – Loopback Controls for Co mmunications Link Fault Isolation – B reak, Parity, Overrun, Framing Error Si mulation D Fully Prioritized Interrupt System Controls D Mode.

Part

TL16C550BI

Description

ACE



Feature


TL16C550B, TL16C550BI ASYNCHRONOUS COMMU NICATIONS ELEMENT D Capable of Running With All Existing TL16C450 Software D After Reset, All Registers Are Identica l to the TL16C450 Register Set D In the FIFO Mode, Transmitter and Receiver Ar e Each Buffered With 16-Byte FIFOs to R educe the Number of Interrupts to the C PU D In the TL16C450 Mode, Hold and Shi ft Registers Elimi.
Manufacture

Texas Instruments

Datasheet
Download TL16C550BI Datasheet




 TL16C550BI
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 562 Kbit/s)
D False-Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous
communications element (ACE). Functionally identical to the TL16C450 on power up (character mode), the
TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive
software overhead.
In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte
in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and
maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY and
TXRDY) have been changed to allow signalling of DMA transfers.
The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report
on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of
transfer operation in progress, the status of the operation, and any error conditions encountered.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TL16C550BI
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
description (continued)
The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These
generators are capable of dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 ×
clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver
logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that
may be software tailored to user requirements to minimize the computing required to handle the
communications link.
The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT)
package. The TL16C550BI is available in a 44-pin PLCC (FN) package.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TL16C550BI
N PACKAGE
(TOP VIEW)
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
RCLK 9
SIN 10
SOUT 11
CS0 12
CS1 13
CS2 14
BAUDOUT 15
XIN 16
XOUT 17
WR1 18
WR2 19
VSS 20
40 VCC
39 RI
38 DCD
37 DSR
36 CTS
35 MR
34 OUT1
33 DTR
32 RTS
31 OUT2
30 INTRPT
29 RXRDY
28 A0
27 A1
26 A2
25 ADS
24 TXRDY
23 DDIS
22 RD2
21 RD1
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
FN PACKAGE
(TOP VIEW)
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
A2
PT PACKAGE
(TOP VIEW)
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
NC – No internal connection
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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