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ACE. TL16C550DI Datasheet

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ACE. TL16C550DI Datasheet






TL16C550DI ACE. Datasheet pdf. Equivalent




TL16C550DI ACE. Datasheet pdf. Equivalent





Part

TL16C550DI

Description

ACE



Feature


TL16C550D, TL16C550DI www.ti.com ...... ....................................... ....................................... ....................................... ....................... SLLS597E – AP RIL 2004 – REVISED DECEMBER 2008 ASYN CHRONOUS COMMUNICATIONS ELEMENT WITH AU TOFLOW CONTROL FEATURES 1 • Programm able Auto-RTS and Auto-CTS • In Auto- CTS Mode, CTS Controls Tra.
Manufacture

Texas Instruments

Datasheet
Download TL16C550DI Datasheet


Texas Instruments TL16C550DI

TL16C550DI; nsmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS • Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop • Capable of Running With All Existing TL16C450 Soft ware • After Reset, All Registers Are Identical to the TL16C450 Register Set • Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC.


Texas Instruments TL16C550DI

= 5 V • Up to 20-MHz Clock Rate for u p to 1.25-Mbaud Operation With VCC = 3. 3 V • Up to 48-MHz Clock Rate for up to 3-Mbaud Operation with VCC = 3.3 V ( ZQS Package Only, Divisor = 1) • Up t o 40-MHz Clock Rate for up to 2.5-Mbaud Operation with VCC = 3.3 V (ZQS Packag e Only, Divisor ≥ 2) • Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC = 2.5 V • In the T.


Texas Instruments TL16C550DI

L16C450 Mode, Hold and Shift Registers E liminate the Need for Precise Synchroni zation Between the CPU and Serial Data • Programmable Baud Rate Generator Al lows Division of Any Input Reference Cl ock by 1 to (216 –1) and Generates an Internal 16× Clock • Standard Asyn chronous Communication Bits (Start, Sto p, and Parity) Added to or Deleted From the Serial Data Stream •.

Part

TL16C550DI

Description

ACE



Feature


TL16C550D, TL16C550DI www.ti.com ...... ....................................... ....................................... ....................................... ....................... SLLS597E – AP RIL 2004 – REVISED DECEMBER 2008 ASYN CHRONOUS COMMUNICATIONS ELEMENT WITH AU TOFLOW CONTROL FEATURES 1 • Programm able Auto-RTS and Auto-CTS • In Auto- CTS Mode, CTS Controls Tra.
Manufacture

Texas Instruments

Datasheet
Download TL16C550DI Datasheet




 TL16C550DI
TL16C550D, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
FEATURES
1
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls Transmitter
In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on the
Same Power Drop
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to the
TL16C450 Register Set
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
Up to 20-MHz Clock Rate for up to 1.25-Mbaud
Operation With VCC = 3.3 V
Up to 48-MHz Clock Rate for up to 3-Mbaud
Operation with VCC = 3.3 V (ZQS Package Only,
Divisor = 1)
Up to 40-MHz Clock Rate for up to 2.5-Mbaud
Operation with VCC = 3.3 V (ZQS Package Only,
Divisor 2)
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 –1) and Generates an Internal 16× Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
5-V, 3.3-V, and 2.5-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 -, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Available in 48-Pin PT, 48-Pin PFB, 32-Pin
RHB, and 24-Pin ZQS Packages
DESCRIPTION/ORDERING INFORMATION
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) of
the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the
TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver
FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software
overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS
input signals.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated




 TL16C550DI
TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE
status at any time. The ACE includes complete modem control capability and a processor interrupt system that
can be tailored to minimize software management of the communications link.
Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of dividing
a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal transmitter
logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates up to a
1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is 6.7 µs (start
bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to TXRDY
and RXRDY, which provide signaling to a DMA controller.
PT/PFB PACKAGE
(TOP VIEW)
RHB PACKAGE
(TOP VIEW)
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
NC - No internal connection
DSR
DCD
RI
VCC
D0
D1
D2
D3
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
12 3 4 5 6 7 8
NC
NC
RD1
VSS
WR1
XOUT
XIN
NC
NC - No internal connection
The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This is
accomplished by eliminating some signals that are not required for some applications. These include the CS0,
CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUT
output signals. There is an internal connection between BAUDOUT and RCLK.
All of the functionality of the TL16C550D is maintained in the RHB package.
ZQS PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
(24-Ball ZQS Package) (continued)
12 3 4 5
(24-Ball ZQS Package)
1
2
3
4
5
A
B
A
D5
D4
D2
D0
VCC
B
D7
D3
D1
MR
C
C
SIN
SOUT
D6
CTS
RTS
D
D
CS2
WR1
RD1 INTRPT
A0
E
E
XIN
XOUT
VSS
A2
A1
TERMINAL ASSIGNMENTS
2
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): TL16C550D TL16C550DI




 TL16C550DI
TL16C550D, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
The TL16C550D is being made available in a reduced pin count package, the 24-pin ZQS package. This is
accomplished by eliminating some signals that are not required for some applications. These include the CS0,
CS1, ADS, RD2, WR2, DSR, RI, DCD, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2,
DTR, and BAUDOUT output signals. There is an internal connection between BAUDOUT and RCLK.
Most of the functionality of the TL16C550D is maintained in the ZQS package, except that which involves the
eliminated signals.
DETAILED DESCRIPTION
Autoflow Control (see Figure 1)
Autoflow control comprises auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the
transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and
notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it
may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
Copyright © 2004–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): TL16C550D TL16C550DI






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