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Dual ACE. TL16C552FN Datasheet

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Dual ACE. TL16C552FN Datasheet






TL16C552FN ACE. Datasheet pdf. Equivalent




TL16C552FN ACE. Datasheet pdf. Equivalent





Part

TL16C552FN

Description

Dual ACE



Feature


ąą TL16C552 DUAL ASYCHRONOUS COMMUNIC ATIONS ELEMENT WITH FIFO SLLS102B − D ECEMBER 1990 − REVISED MARCH 1996 D IBM PC/AT  Compatible D Two TL16C550 ACEs D Enhanced Bidirectional Printer Port D 16-Byte FIFOs Reduce CPU Interru pts D Independent Control of Transmit, Receive, Line Status, and Data Set Inte rrupts on Each Channel D Individual Mod em Control Signals for Eac.
Manufacture

Texas Instruments

Datasheet
Download TL16C552FN Datasheet


Texas Instruments TL16C552FN

TL16C552FN; h Channel D Programmable Serial Interfa ce Characteristics for Each Channel: 5-, 6-, 7-, or 8-bit Characters − E ven-, Odd-, or No-Parity Bit Generation and Detection − 1-, 1 1/2-, or 2-Sto p Bit Generation D 3-State TTL Drive fo r the Data and Control Bus on Each Chan nel D Hardware and Software Compatible With TL16C452 description FN PACKAGE (TOP VIEW) RXRDY0 DCD1 .


Texas Instruments TL16C552FN

GND RI1 DSR1 CLK CS1 TRI PEMD ACK PE BUS Y SLCT VDD ERR SIN1 RXRDY1 SOUT1 DTR1 RTS1 CTS1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 D B7 TXRDY0 VDD RTS0 DTR0 SOUT0 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 2 5 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 .


Texas Instruments TL16C552FN

41 42 43 INT1 INT2 SLIN INIT AFD STB GN D PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 INT0 BDO GND CTS0 DCD0 RI0 DSR0 CS0 A2 A1 A 0 IOW IOR CS2 RESET VDD SIN0 TXRDY1 ENI RQ description The TL16C552 is an enha nced dual channel version of the popula r TL16C550 asynchronous communications element (ACE). The device serves two se rial input/output interfaces simultaneo usly in microcompu.

Part

TL16C552FN

Description

Dual ACE



Feature


ąą TL16C552 DUAL ASYCHRONOUS COMMUNIC ATIONS ELEMENT WITH FIFO SLLS102B − D ECEMBER 1990 − REVISED MARCH 1996 D IBM PC/AT  Compatible D Two TL16C550 ACEs D Enhanced Bidirectional Printer Port D 16-Byte FIFOs Reduce CPU Interru pts D Independent Control of Transmit, Receive, Line Status, and Data Set Inte rrupts on Each Channel D Individual Mod em Control Signals for Eac.
Manufacture

Texas Instruments

Datasheet
Download TL16C552FN Datasheet




 TL16C552FN
ąą
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
D IBM PC/AT Compatible
D Two TL16C550 ACEs
D Enhanced Bidirectional Printer Port
D 16-Byte FIFOs Reduce CPU Interrupts
D Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
D Individual Modem Control Signals for Each
Channel
D Programmable Serial Interface
Characteristics for Each Channel:
− 5-, 6-, 7-, or 8-bit Characters
− Even-, Odd-, or No-Parity Bit Generation
and Detection
− 1-, 1 1/2-, or 2-Stop Bit Generation
D 3-State TTL Drive for the Data and Control
Bus on Each Channel
D Hardware and Software Compatible With
TL16C452
description
FN PACKAGE
(TOP VIEW)
SOUT1
DTR1
RTS1
CTS1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
TXRDY0
VDD
RTS0
DTR0
SOUT0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
INT1
INT2
SLIN
INIT
AFD
STB
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BDO
description
The TL16C552 is an enhanced dual channel version of the popular TL16C550 asynchronous communications
element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM PC/AT is a trademark of International Business Machines Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1




 TL16C552FN
TL16C552
ą
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (216 − 1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
28
CTS0
31
DSR0
29
DCD0
RI0 30
SIN0 41
CS0 32
14 −21
DB −DB7
CTS1 13
DSR1 5
DCD1 8
RI1 6
SIN1 62
CS1 3
8
8
ACE
#1
ACE
#2
24
RTS0
25
DTR0
26
SOUT0
45 INT0
9 RXRDY0
22 TXRDY0
12 RTS1
11 DTR1
10 SOUT1
60 INT1
61 RXRDY1
42 TXRDY1
A0 −A2 35 −33
IOW 36
IOR 37
RESET 39
CLK 4
Select
and
Control
Logic
8
63
ERR
65
SLCT
BUSY 66
67
PE
ACK 68
PEMD 1
CS2 38
ENIRQ 43
Parallel
Port
44
BDO
8 53 −46 PD0 −PD7
57 INIT
56 AFD
55 STB
58 SLIN
59 INT2
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443




 TL16C552FN
ą
TERMINAL
NAME
NO.
ACK
68
AFD
56
A0, A1, A2
35, 34, 33
BDO
44
BUSY
66
CLK
CS0, CS1, CS2
4
32, 3, 38
CTS0, CTS1
28, 13
DB0 − DB7
14 − 21
DCD0, DCD1
29, 8
DSR0, DSR1
31, 5
DTR0, DTR1
25, 11
ENIRQ
43
ERR
GND
INIT
IOR
63
7, 27, 54
57
37
IOW
36
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
Terminal Functions
I/O
DESCRIPTION
I
Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.
I/O Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to VDD of approximately 10 k.
I
Address lines A0 −A2. A0, A1, and A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.
O Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the
parallel port is read. This output can control the system bus driver (74LS245).
I
Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.
I
Clock input. CLK is an external clock input to the baud rate divisor of each ACE.
I
Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port.
I
Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTS terminal, since the previous reading of the associated modem status register,
causes the setting of delta clear to send (CTS) bit (MSR0) of each modem status register.
I/O Data bits DB0 − DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,
and status information between the TL16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the
first serial data bit to be received or transmitted.
I
Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or DCD) bit
of the modem status register indicates whether the DCD input has changed states since the
previous reading of the modem status register. DCD has no affect on the receiver.
I
Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated
modem status register. The MSR1 (delta data set ready or DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
register.
O Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register
bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.
I
Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status
register. INT2 is latched high on rising edge of ACK.
I
Line printer error. ERR is an input line from the printer. The printer reports an error by holding this
line low during the error condition.
Ground (0 V). All terminals must be tied to ground for proper operation.
I/O Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer initialization routine to be started. This terminal has an internal pullup
resistor to VDD of approximately 10 k.
I
Input/output read strobe. IOR is an active-low input that enables the selected channel to output
data to the data bus (DB0 −DB7). The data output depends upon the register selected by the
address inputs A0, A1, A2, and chip select. Chip select 0 (CS0) selects ACE #1, chip select 1 (CS1)
selects ACE #2, and chip select 2 (CS2) selects the printer port.
I
Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to
either ACE or to the parallel port. The destination depends upon the register selected by the address
inputs A0, A1, A2, and chip selects CS0, CS1, and CS2.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
3



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