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ACE. TL16C554I Datasheet

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ACE. TL16C554I Datasheet






TL16C554I ACE. Datasheet pdf. Equivalent




TL16C554I ACE. Datasheet pdf. Equivalent





Part

TL16C554I

Description

ACE



Feature


ąą TL16C554, TL16C554I ASYNCHRONOUS C OMMUNICATIONS ELEMENT ą SLLS165G − J ANUARY 1994 − REVISED MARCH 2006 D I ntegrated Asynchronous Communications E lement D Consists of Four Improved TL16 C550 ACEs Plus Steering Logic D In FIFO Mode, Each ACE Transmitter and Receive r Is Buffered With 16-Byte FIFO to Redu ce the Number of Interrupts to CPU D In TL16C450 Mode, Hold and .
Manufacture

Texas Instruments

Datasheet
Download TL16C554I Datasheet


Texas Instruments TL16C554I

TL16C554I; Shift Registers Eliminate Need for Preci se Synchronization Between the CPU and Serial Data D Up to 16-MHz Clock Rate f or up to 1-Mbaud Operation D Programmab le Baud Rate Generators Which Allow Div ision of Any Input Reference Clock by 1 to (216ā −ā 1) and Generate an Int ernal 16 × Clock D Adds or Deletes Sta ndard Asynchronous Communication Bits ( Start, Stop, and Parity.


Texas Instruments TL16C554I

) to or From the Serial Data Stream D In dependently Controlled Transmit, Receiv e, Line Status, and Data Set Interrupts D Fully Programmable Serial Interface Characteristics: − 5-, 6-, 7-, or 8- Bit Characters − Even-, Odd-, or No-P arity Bit − 1-, 1 1/2-, or 2-Stop Bit Generation − Baud Generation (DC to 1-Mbit Per Second) D False Start Bit De tection D Complete Status .


Texas Instruments TL16C554I

Reporting Capabilities D Line Break Gene ration and Detection D Internal Diagnos tic Capabilities: − Loopback Controls for Communications Link Fault Isolatio n − Break, Parity, Overrun, Framing E rror Simulation D Fully Prioritized Int errupt System Controls D Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) D 3-State Outputs Provide TTL Driv e Capabilities for Bid.

Part

TL16C554I

Description

ACE



Feature


ąą TL16C554, TL16C554I ASYNCHRONOUS C OMMUNICATIONS ELEMENT ą SLLS165G − J ANUARY 1994 − REVISED MARCH 2006 D I ntegrated Asynchronous Communications E lement D Consists of Four Improved TL16 C550 ACEs Plus Steering Logic D In FIFO Mode, Each ACE Transmitter and Receive r Is Buffered With 16-Byte FIFO to Redu ce the Number of Interrupts to CPU D In TL16C450 Mode, Hold and .
Manufacture

Texas Instruments

Datasheet
Download TL16C554I Datasheet




 TL16C554I
ąą
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
ą
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
D Integrated Asynchronous Communications
Element
D Consists of Four Improved TL16C550 ACEs
Plus Steering Logic
D In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
D In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
D Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
D Programmable Baud Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216ā ā 1) and
Generate an Internal 16 × Clock
D Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
D Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D Fully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (DC to 1-Mbit Per
Second)
D False Start Bit Detection
D Complete Status Reporting Capabilities
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D 3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
description
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the operation performed and
any error conditions encountered.
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and
(216 −1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and
in an 80-pin (TQFP) PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1994 − 2006, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TL16C554I
TL16C554, TL16C554I
ą
ASYNCHRONOUS COMMUNICATIONS ELEMENT
ą
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
FN PACKAGE
(TOP VIEW)
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC − No internal connection
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TL16C554I
ą
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
ą
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
PN PACKAGE
(TOP VIEW)
NC
DSRC
CTSC
DTRC
VCC
RTSC
INTC
CSC
TXC
IOR
NC
TXD
CSD
INTD
RTSD
GND
DTRD
CTSD
DSRD
NC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
71
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC
DSRB
CTSB
DTRB
GND
RTSB
INTB
CSB
TXB
IOW
NC
TXA
CSA
INTA
RTSA
VCC
DTRA
CTSA
DSRA
NC
NC − No internal connection
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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