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DUAL UART. TL16C2550 Datasheet

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DUAL UART. TL16C2550 Datasheet






TL16C2550 UART. Datasheet pdf. Equivalent




TL16C2550 UART. Datasheet pdf. Equivalent





Part

TL16C2550

Description

DUAL UART



Feature


www.ti.com TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 1.8-V t o 5-V DUAL UART WITH 16-BYTE FIFOS Chec k for Samples: TL16C2550 FEATURES 1 Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transm itter • In Auto-RTS Mode, RCV FIFO Co ntents, and Threshold Control RTS • S erial and Modem Control Outputs Drive a RJ11 Cable Directly When Equi.
Manufacture

Texas Instruments

Datasheet
Download TL16C2550 Datasheet


Texas Instruments TL16C2550

TL16C2550; pment Is on the Same Power Drop • Capa ble of Running With All Existing TL16C4 50 Software • After Reset, All Regist ers Are Identical to the TL16C450 Regis ter Set • Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V • Up to 20-MHz Clock Rate for up t o 1.25-Mbaud Operation With VCC = 3.3 V • Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC =.


Texas Instruments TL16C2550

2.5 V • Up to 10-MHz Clock Rate for u p to 625-kbaud Operation With VCC = 1.8 V • In the TL16C450 Mode, Hold and S hift Registers Eliminate the Need for P recise Synchronization Between the CPU and Serial Data • Programmable Baud R ate Generator Allows Division of Any In put Reference Clock by 1 to (2 16 -1) a nd Generates an Internal 16 × Clock Standard Asynchronous Com.


Texas Instruments TL16C2550

munication Bits (Start, Stop, and Parity ) Added to or Deleted From the Serial D ata Stream • 5-V, 3.3-V, 2.5-V, and 1 .8-V Operation • Independent Receiver Clock Input • Transmit, Receive, Lin e Status, and Data Set Interrupts Indep endently Controlled • Fully Programma ble Serial Interface Characteristics: 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit .

Part

TL16C2550

Description

DUAL UART



Feature


www.ti.com TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 1.8-V t o 5-V DUAL UART WITH 16-BYTE FIFOS Chec k for Samples: TL16C2550 FEATURES 1 Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transm itter • In Auto-RTS Mode, RCV FIFO Co ntents, and Threshold Control RTS • S erial and Modem Control Outputs Drive a RJ11 Cable Directly When Equi.
Manufacture

Texas Instruments

Datasheet
Download TL16C2550 Datasheet




 TL16C2550
www.ti.com
TL16C2550
SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
Check for Samples: TL16C2550
FEATURES
1
• Programmable Auto-RTS and Auto-CTS
• In Auto-CTS Mode, CTS Controls Transmitter
• In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
• Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on the
Same Power Drop
• Capable of Running With All Existing
TL16C450 Software
• After Reset, All Registers Are Identical to the
TL16C450 Register Set
• Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
• Up to 20-MHz Clock Rate for up to 1.25-Mbaud
Operation With VCC = 3.3 V
• Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
• Up to 10-MHz Clock Rate for up to 625-kbaud
Operation With VCC = 1.8 V
• In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(2 16 -1) and Generates an Internal 16 × Clock
• Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
• 5-V, 3.3-V, 2.5-V, and 1.8-V Operation
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
• Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbit/s)
• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection Internal
Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Available in 48-Pin TQFP (PFB) Package, 32-
Pin QFN (RHB), or 44-Pin PLCC (FN) Package
• Pin Compatible with TL16C752B (48-Pin
Package PFB)
APPLICATIONS
• Point-of-Sale Terminals
• Gaming Terminals
• Portable Applications
• Router Control
• Cellular Data
• Factory Automation
DESCRIPTION
The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the uart function is Asynchronous
Communications Element (ACE), and these terms will
be used interchangeably. The bulk of this document
describes the behavior of each ACE, with the
understanding that two such devices are incorporated
into the TL16C2550.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2012, Texas Instruments Incorporated




 TL16C2550
TL16C2550
SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode),
each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by
buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their
respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input,
thus eliminating overruns in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on
data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status
of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt
system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors from
1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE
accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would
generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at
24 MHz.
Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.
PFB PACKAGE
(TOP VIEW)
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
TL16C2550PFB
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
NC - No internal connection
2
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Copyright © 2005–2012, Texas Instruments Incorporated




 TL16C2550
www.ti.com
FN PACKAGE
(TOP VIEW)
TL16C2550
SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012
6 5 4 3 2 1 44 43 42 41 40
D5 7
D6 8
D7 9
RXB 10
RXA 11
TXRDYB 12
TXA 13
TXB 14
OPB 15
CSA 16
CSB 17
TL16C2550FN
39 RESET
38 DTRB
37 DTRA
36 RTSA
35 OPA
34 RXRDYA
33 INTA
32 INTB
31 A0
30 A1
29 A2
18 19 20 21 22 23 24 25 26 27 28
RHB PACKAGE
(TOP VIEW)
D6 1
D7 2
RXB 3
RXA 4
TXA 5
TXB 6
CSA 7
CSB 8
TL16C2550RHB
24 RESET
23 RTSA
22 INTA
21 INTB
20 A0
19 A1
18 A2
17 NC
NC - No internal connection
The 32-pin RHB package does not provide access to DSRA, DSRB, RIA, RIB, CDA, CDB inputs, and OPA, OPB,
RXRDYA, RXRDYB, TXRDYA, TXRDYB, DTRA, DTRB outputs.
Copyright © 2005–2012, Texas Instruments Incorporated
Product Folder Links :TL16C2550
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3






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