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DUAL UART. TL16C2552 Datasheet







TL16C2552 UART. Datasheet pdf. Equivalent






Part

TL16C2552

Description

DUAL UART

Manufacture

Texas Instruments

Datasheet
Download TL16C2552 Datasheet


Texas Instruments TL16C2552

TL16C2552; TL16C2552 www.ti.com SLWS163A – SEPT EMBER 2005 – REVISED JUNE 2006 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS FE ATURES • Programmable Auto-RTS and Au to-CTS • In Auto-CTS Mode, CTS Contro ls the Transmitter • In Auto-RTS Mode , RCV FIFO Contents, and Threshold Cont rol RTS • Serial and Modem Control Ou tputs Drive a RJ11 Cable Directly When Equipment is on the Same Power.


Texas Instruments TL16C2552

Drop • Capable of Running With All Ex isting TL16C450 Software • After Rese t, All Registers Are Identical to the T L16C450 Register Set • Up to 24-MHz C lock Rate for up to 1.5-Mbaud Operation With VCC = 5 V • Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation Wit h VCC = 3.3 V • Up to 16-MHz Clock Ra te for up to 1-Mbaud Operation With VCC = 2.5 V • Up to 10-MHz Cloc k Rate for up to 625-kbaud Operation Wit h VCC = 1.8 V • In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Betwe en the CPU and Serial Data • Programm able Baud Rate Generator Allows Divisio n of Any Input Reference Clock by 1 to (216 - 1) and Generates an Internal 16 × Clock • Standard Asynchronous Comm unication Bits (Start, St.



Part

TL16C2552

Description

DUAL UART

Manufacture

Texas Instruments

Datasheet
Download TL16C2552 Datasheet




 TL16C2552
TL16C2552
www.ti.com
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
FEATURES
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls the
Transmitter
In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment is on
the Same Power Drop
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to the
TL16C450 Register Set
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
Up to 20-MHz Clock Rate for up to
1.25-Mbaud Operation With VCC = 3.3 V
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
Up to 10-MHz Clock Rate for up to 625-kbaud
Operation With VCC = 1.8 V
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 - 1) and Generates an Internal 16 × Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
5-V, 3.3-V, 2.5-V, and 1.8 V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 ½-, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Available in 44-Pin PLCC (FN) or 32-Pin QFN
(RHB) Packages
Each UART's Internal Register Set May Be
Written Concurrently to Save Setup Time
Multi-Function Output (MF) Allows Users to
Select Among Several Functions, Saving
Package Pins
APPLICATIONS
Point-of-Sale Terminals
Gaming Terminals
Portable Applications
Router Control
Cellular Data
Factory Automation
DESCRIPTION
The TL16C2552 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the UART function is
Asynchronous Communications Element (ACE), and
these terms will be used interchangeably. The bulk
of this document describes the behavior of each
ACE, with the understanding that two such devices
are incorporated into the TL16C2552.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated





 TL16C2552
TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional
upgrade of the TL16C450. Functionally equivalent to
the TL16C450 on power up or reset (single character
or TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three
additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS output
and CTS input, thus eliminating overruns in the
receive FIFO.
Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control
capability and a processor interrupt system that can
be tailored to the application.
Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors of from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a
1.5-Mbaud serial data rate (24-MHz input clock). As
a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1
serial data), with the internal clock running at 24
MHz.
Each ACE has a TXRDY and RXRDY output that
can be used to interface to a DMA controller.
FN PACKAGE
(TOP VIEW)
www.ti.com
6 5 4 3 2 1 44 43 42 41 40
D5 7
D6 8
D7 9
A0 10
XTAL1 11
GND 12
XTAL2 13
A1 14
A2 15
CHSEL 16
INTB 17
TL16C2552FN
39 RXA
38 TXA
37 DTRA
36 RTSA
35 MFA
34 INTA
33 VCC
32 TXRDYB
31 RIB
30 CDB
29 DSRB
18 19 20 21 22 23 24 25 26 27 28
RHB PACKAGE
(TOP VIEW)
D6 1
D7 2
A0 3
XTAL1 4
XTAL2 5
A1 6
A2 7
CHSEL 8
TL16C2552RHB
24 RXA
23 TXA
22 RTSA
21 INTA
20 GND
19 NC
18 NC
17 CTSB
NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA, DTRB,
TXRDYA, TXRDYB outputs.
2
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