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ACE. TL16C450 Datasheet

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ACE. TL16C450 Datasheet






TL16C450 ACE. Datasheet pdf. Equivalent




TL16C450 ACE. Datasheet pdf. Equivalent





Part

TL16C450

Description

ACE



Feature


TL16C450 ASYNCHRONOUS COMMUNICATIONS ELE MENT SLLS037C − MARCH 1988 − REVIS ED JANUARY 2006 D Programmable Baud Ra te Generator Allows Division of Any Inp ut Reference Clock by 1 to (216 −1) a nd Generates an Internal 16 × Clock N PACKAGE (TOP VIEW) D0 1 D1 2 40 VCC 39 RI D Full Double Buffering Eliminat es the Need for Precise Synchronization D Standard Asynchronous .
Manufacture

Texas Instruments

Datasheet
Download TL16C450 Datasheet


Texas Instruments TL16C450

TL16C450; Communication D2 3 D3 4 D4 5 D5 6 38 D CD 37 DSR 36 CTS 35 MR Bits (Start, St op, and Parity) Added or Deleted to or From the Serial Data Stream D6 7 D7 8 34 OUT1 33 DTR D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data RCLK 9 SIN 10 SOUT 11 32 RTS 31 OUT2 30 INTRPT Set Interru pts Independently Controlled CS0 12 29 NC D Fully Progr.


Texas Instruments TL16C450

ammable Serial Interface Characteristics : − 5-, 6 -, 7 -, or 8-Bit Characters − Even-, Odd -, or No-Parity Bit Gen eration and Detection − 1-, 1 1/2 -, or 2-Stop Bit Generation − Baud Gener ation (dc to 256 Kbit/s) D False Start Bit Detection D Complete Status Reporti ng Capabilities CS1 13 CS2 14 BAUDOUT 15 XTAL1 16 XTAL2 17 DOSTR 18 DOSTR 19 VSS 20 28 A0 27 A1 26 A2 .


Texas Instruments TL16C450

25 ADS 24 CSOUT 23 DDIS 22 DISTR 21 DIST R NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please cont act your local distributor or TI Sales Office for more information. D 3-State TTL Drive Capabilities for Bidirection al Data Bus and Control Bus FN PACKAGE (TOP VIEW) D4 D3 D2 D1 D0 NC VCC RI D CD DSR CTS D Line Break Generation and Detection D Inte.

Part

TL16C450

Description

ACE



Feature


TL16C450 ASYNCHRONOUS COMMUNICATIONS ELE MENT SLLS037C − MARCH 1988 − REVIS ED JANUARY 2006 D Programmable Baud Ra te Generator Allows Division of Any Inp ut Reference Clock by 1 to (216 −1) a nd Generates an Internal 16 × Clock N PACKAGE (TOP VIEW) D0 1 D1 2 40 VCC 39 RI D Full Double Buffering Eliminat es the Need for Precise Synchronization D Standard Asynchronous .
Manufacture

Texas Instruments

Datasheet
Download TL16C450 Datasheet




 TL16C450
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 −1) and Generates an Internal 16 ×
Clock
N PACKAGE
(TOP VIEW)
D0 1
D1 2
40 VCC
39 RI
D Full Double Buffering Eliminates the Need
for Precise Synchronization
D Standard Asynchronous Communication
D2 3
D3 4
D4 5
D5 6
38 DCD
37 DSR
36 CTS
35 MR
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream
D6 7
D7 8
34 OUT1
33 DTR
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
RCLK 9
SIN 10
SOUT 11
32 RTS
31 OUT2
30 INTRPT
Set Interrupts Independently Controlled
CS0 12 29 NC
D Fully Programmable Serial Interface
Characteristics:
− 5-, 6 -, 7 -, or 8-Bit Characters
− Even-, Odd -, or No-Parity Bit Generation
and Detection
− 1-, 1 1/2 -, or 2-Stop Bit Generation
− Baud Generation (dc to 256 Kbit/s)
D False Start Bit Detection
D Complete Status Reporting Capabilities
CS1 13
CS2 14
BAUDOUT 15
XTAL1 16
XTAL2 17
DOSTR 18
DOSTR 19
VSS 20
28 A0
27 A1
26 A2
25 ADS
24 CSOUT
23 DDIS
22 DISTR
21 DISTR
NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please
contact your local distributor or TI Sales Office for more information.
D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
FN PACKAGE
(TOP VIEW)
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Easily Interfaces to Most Popular
Microprocessors
D Faster Plug-In Replacement for National
Semiconductor NS16C450
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
NC
A0
A1
A2
Please be aware that an important notice concerningNaCv−ailNaobiilnittye,rnsatal ncdoannrdecwtiaonrranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1988 − 2006, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TL16C450
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
description
The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions
in a microcomputer system as a serial input/output interface.
The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the
ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 −1) and producing a 16× clock for driving the internal
transmitter logic. Provisions are included to use this 16 × clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TL16C450
block diagram
2−9
D7 −D0
Data
Bus
Buffer
Internal
Data Bus
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
Receiver
Buffer
Register
Receiver
Shift
Register
11 SIN
Line
Control
Register
Divisor
Latch (LS)
A0 31
A1 30
A2 29
CS0 14
CS1 15
CS2 16
ADS 28
MR 39
DISTR 25
DISTR 24
DOSTR 21
DOSTR 20
DDIS 26
CSOUT 27
XTAL1 18
XTAL2 19
Select
and
Control
Logic
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
44
VCC 22
VSS
Power
Supply
Terminal numbers shown are for the FN package.
Interrupt
Enable
Register
Interrupt
I/O
Register
Baud
Generator
Interrupt
Control
Logic
Receiver
Timing and
Control
10 RCLK
17 BAUDOUT
Transmitter
Timing and
Control
Transmitter
Shift
Register
13 SOUT
Modem
Control
Logic
36 RTS
40 CTS
37 DTR
41 DSR
42 DCD
43 RI
38 OUT1
35 OUT2
33
INTRPT
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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