TL16C450FN

TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS037C − MARCH 1988 − REVISED JANUARY 2006 D Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 16 × Clock N PACKAGE (TOP VIEW) D0 1 D1 2 40 VCC 39 RI D Full Double Buffering Eliminates the Need for Precise Synchronization D Standard Asynchronous Communication D2 3 D3 4 D4 5 D5 6 38 DCD 37 DSR 36 CTS 35 MR Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream D6 7 D7 8 34 OUT1 33 DTR D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data RCLK 9 SIN 10 SOUT 11 32 RTS 31 OUT2 30 INTRPT Set Interrupts Independently Controlled CS0 12 29 NC D Fully Programmable Serial Interface Characteristics: − 5-, 6 -, 7 -, or 8-Bit Characters − Even-, Odd -, or No-Parity Bit Generation and Detection − 1-, 1 1/2 -, or 2-Stop Bit Generation − Baud Generation (dc to 256 Kbit/s) D False Start Bit Detection D Complete Status Reporting Capabilities CS1 13 CS2 14 BAUDOUT 15 XTAL1 16 XTAL2 17 DOSTR 18 DOSTR 19 VSS 20 28 A0 27 A1 26 A2 25 ADS 24 CSOUT 23 DDIS 22 DISTR 21 DISTR NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please contact your local distributor or TI Sales Office for more information. D 3-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus FN PACKAGE (TOP VIEW) D4 D3 D2 D1 D0 NC VCC RI DCD DSR CTS D Line Break Generation and Detection D Internal Diagnostic Capa...