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DUAL UART. TL16C752D Datasheet

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DUAL UART. TL16C752D Datasheet







TL16C752D UART. Datasheet pdf. Equivalent




TL16C752D UART. Datasheet pdf. Equivalent





Part

TL16C752D

Description

DUAL UART

Manufacture

Texas Instruments

Datasheet
Download TL16C752D Datasheet


Texas Instruments TL16C752D

TL16C752D; Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TL16C752D SLLSEN8C – SEPTEMBE R 2015 – REVISED JUNE 2017 TL16C752D Dual UART With 64-Byte FIFO 1 Features •1 Pin Compatible With TL16C2550 Wit h Enhanced Features Provided Through an Improved FIFO Register • Supports Wi de Supply Voltage Range of 1.62 V to 5. 5 V – 3 Mbps (48-MHz Oscil.


Texas Instruments TL16C752D

lator Input Clock) at 5 V – 3 Mbps (48 -MHz Oscillator Input Clock) at 3.3 V 1.5 Mbps (24-MHz Oscillator Input Cl ock) at 2.5 V – 1 Mbps (16-MHz Oscill ator Input Clock) at 1.8 V • Characte rized for Operation from –40°C to 85 °C • 64-Byte Transmit/Receive FIFO Software-Selectable Baud-Rate Genera tor • Programmable and Selectable Tra nsmit and Receive FIFO Trigger Level.


Texas Instruments TL16C752D

s for DMA, Interrupt Generation, and Sof tware or Hardware Flow Control • Soft ware/Hardware Flow Control – Programm able Xon and Xoff Characters With Optio nal Xon Any Character – Programmable Auto-RTS and Auto-CTSModem Control Func tions (CTS, RTS, DSR, DTR, RI, and CD) • DMA Signaling Capability for Both R eceived and Transmitted Data on PN Pack age • RS-485 Mode Support .



Part

TL16C752D

Description

DUAL UART

Manufacture

Texas Instruments

Datasheet
Download TL16C752D Datasheet




 TL16C752D
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
TL16C752D
SLLSEN8C – SEPTEMBER 2015 – REVISED JUNE 2017
TL16C752D Dual UART With 64-Byte FIFO
1 Features
1 Pin Compatible With TL16C2550 With Enhanced
Features Provided Through an Improved FIFO
Register
• Supports Wide Supply Voltage Range of 1.62 V to
5.5 V
– 3 Mbps (48-MHz Oscillator Input Clock)
at 5 V
– 3 Mbps (48-MHz Oscillator Input Clock)
at 3.3 V
– 1.5 Mbps (24-MHz Oscillator Input Clock)
at 2.5 V
– 1 Mbps (16-MHz Oscillator Input Clock)
at 1.8 V
• Characterized for Operation from –40°C to 85°C
• 64-Byte Transmit/Receive FIFO
• Software-Selectable Baud-Rate Generator
• Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA, Interrupt
Generation, and Software or Hardware Flow
Control
• Software/Hardware Flow Control
– Programmable Xon and Xoff Characters With
Optional Xon Any Character
– Programmable Auto-RTS and Auto-CTS-
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
• DMA Signaling Capability for Both Received and
Transmitted Data on PN Package
• RS-485 Mode Support
• Infrared Data Association (IrDA) Capability
• Programmable Sleep Mode
• Programmable Serial Interface Characteristics
– 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2
Stop Bit Generation
– Even, Odd, or No Parity Bit Generation and
Detection
• False Start Bit and Line Break Detection
• Internal Test and Loopback Capabilities
• SC16C752B and XR16M752 Pin Compatible With
Additional Enhancements
2 Applications
• Automotive Infotainment
• Mobile Devices
• Communications Equipment
• White Goods
• Industrial Computing
3 Description
The TL16C752D is a dual universal asynchronous
receiver transmitter (UART) with 64-byte FIFOs,
automatic hardware and software flow control, and
data rates up to 3 Mbps. The device offers enhanced
features. It has a transmission character control
register (TCR) that stores received FIFO threshold
level to start or stop transmission during hardware
and software flow control.
With the FIFO RDY register, the software gets the
status of TXRDY or RXRDY for all two ports in one
access. On-chip status registers provide the user with
error indications, operational status, and modem
interface control. System interrupts may be tailored to
meet user requirements. An internal loop-back
capability allows onboard diagnostics. The
TL16C752D incorporates the functionality of two
UARTs, each UART having its own register set and
FIFOs.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
TL16C752D
TQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
A2 to A0
D7 to D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
Data Bus
Interface
Crystal
Oscillator
Buffer
UART Channel A
64-Byte TX FIFO TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
TXA
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
RXA
UART Channel B
64-Byte TX FIFO TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
TXB
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
RXB
VCC
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.





 TL16C752D
TL16C752D
SLLSEN8C – SEPTEMBER 2015 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configurations and Function ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements ................................................ 9
7.7 Typical Characteristics ............................................ 14
8 Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 26
8.5 Register Maps ......................................................... 28
9 Application and Implementation ........................ 44
9.1 Application Information............................................ 44
9.2 Typical Application .................................................. 44
10 Power Supply Recommendations ..................... 47
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Examples................................................... 48
12 Device and Documentation Support ................. 49
12.1 Community Resources.......................................... 49
12.2 Trademarks ........................................................... 49
12.3 Electrostatic Discharge Caution ............................ 49
12.4 Glossary ................................................................ 49
13 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Revision B (March 2016) to Revision C
Page
• Changed Feature From: 2 Mbps (32-MHz Oscillator Input Clock) at 3.3 V To: 3 Mbps (48-MHz Oscillator Input
Clock) at 3.3 V ........................................................................................................................................................................ 1
• Changed Feature From: Characterized for Operation from 0°C to 70°C To: Characterized for Operation from –40°C
to 85°C ................................................................................................................................................................................... 1
• Removed pin 35 from NC in the Pin Functions table ............................................................................................................. 4
• Changed Operating free-air temperature From: MIN = 0, MAX = 70 To: MIN = –40, MAX = 85 in the Absolute
Maximum Ratings ................................................................................................................................................................... 5
• Changed Oscillator or clock speed MAX value From: 32 MHz To: 48 MHz in the Recommended Operating Conditions .... 6
• Changed CP clock period (3.3 V) values From: MIN = 32, MAX = 32 To: MIN = 20, MAX = 48 ns in the Timing
Requirements ......................................................................................................................................................................... 9
Changes from Revision A (October 2015) to Revision B
Page
• Changed the Device Information table Body Size column From: 3.67 mm x 3.67 mm To: 7.00 mm x 7.00 mm .................. 1
Changes from Original (September 2015) to Revision A
Page
• Changed VOL MAX value in the VCC = 5 V section of Electrical Characteristics From: 0.4 V To: 0.5 V ................................ 8
2
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Copyright © 2015–2017, Texas Instruments Incorporated





 TL16C752D
www.ti.com
TL16C752D
SLLSEN8C – SEPTEMBER 2015 – REVISED JUNE 2017
5 Description (continued)
The two UARTs share only the data bus interface and clock source, otherwise they operate independently.
Another name for the UART function is asynchronous communications element (ACE), and these terms are used
interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two
such devices are incorporated into the TL16C752D device.
6 Pin Configurations and Function
PFB Package
48-Pin TQFP
Top View
48 47 46 45 44 43 42 41 40 39 38 37
D5 1
D6 2
D7 3
RXB 4
RXA 5
TXRDYB 6
TXA 7
TXB 8
OPB 9
CSA 10
CSB 11
NC 12
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OPA
31 RXRDYA
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
N.C. – No internal connection
Pin Functions
PIN
I/O
NAME
TQFP
DESCRIPTION
A0
28
I Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map.
A1
27
I Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map.
A2
26
I Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
CDA, CDB
40, 16
I
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A
low on these pins indicates that a carrier has been detected by the modem for that channel.
CSA, CSB
10, 11
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
I TL16C752D for the channel or channels addressed. Individual UART sections (A and B) are
addressed by providing a low on the respective CSA and CSB pin.
CTSA, CTSB
38, 23
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
I TL16C752D device. Status can be checked by reading MSR[4]. These pins only affect the transmit
and receive operations when auto CTS function is enabled through the enhanced feature register
(EFR[7]), for hardware flow control operation.
D0–D4,
D5–D7
44 to 48,
1 to 3
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or
from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
serial data stream.
DSRA, DSRB
39, 20
Data set ready (active low). These inputs are associated with individual UART channels A through B.
I A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: TL16C752D
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