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DUAL UART. TL16C754B Datasheet

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DUAL UART. TL16C754B Datasheet






TL16C754B UART. Datasheet pdf. Equivalent




TL16C754B UART. Datasheet pdf. Equivalent





Part

TL16C754B

Description

DUAL UART



Feature


TL16C754B QUAD UART WITH 64ĆBYTE FIFO D ST16C654 Pin Compatible With Addition al Enhancements D Supports Up To 24-MHz Crystal Input Clock ( 1.5 Mbps) D Supp orts Up To 48-MHz Oscillator Input Cloc k ( 3 Mbps) for 5-V Operation D Support s Up To 32-MHz Oscillator Input Clock ( 2 Mbps) for 3.3-V Operation D 64-Byte Transmit FIFO D 64-Byte Receive FIFO Wi th Error Flags D Pr.
Manufacture

Texas Instruments

Datasheet
Download TL16C754B Datasheet


Texas Instruments TL16C754B

TL16C754B; ogrammable and Selectable Transmit and R eceive FIFO Trigger Levels for DMA and Interrupt Generation D Programmable Rec eive FIFO Trigger Levels for Software/H ardware Flow Control D Software/Hardwar e Flow Control − Programmable Xon/Xof f Characters − Programmable Auto-RTS and Auto-CTS D Optional Data Flow Resum e by Xon Any Character D DMA Signalling Capability for Both R.


Texas Instruments TL16C754B

eceived and Transmitted Data D Supports 3.3-V or 5-V Supply SLLS397A − NOVEM BER 1999 − REVISED JUNE 2004 D Charac terized for Operation From −40°C to 85°C D Software Selectable Baud Rate G enerator D Prescalable Provides Additio nal Divide by 4 Function D Fast Access 2 Clock Cycle IOR/IOW Pulse Width D Pro grammable Sleep Mode D Programmable Ser ial Interface Characterist.


Texas Instruments TL16C754B

ics − 5, 6, 7, or 8-Bit Characters − Even, Odd, or No Parity Bit Generation and Detection − 1, 1.5, or 2 Stop Bi t Generation D False Start Bit Detectio n D Complete Status Reporting Capabilit ies in Both Normal and Sleep Mode D Lin e Break Generation and Detection D Inte rnal Test and Loopback Capabilities D F ully Prioritized Interrupt System Contr ols D Modem Control Func.

Part

TL16C754B

Description

DUAL UART



Feature


TL16C754B QUAD UART WITH 64ĆBYTE FIFO D ST16C654 Pin Compatible With Addition al Enhancements D Supports Up To 24-MHz Crystal Input Clock ( 1.5 Mbps) D Supp orts Up To 48-MHz Oscillator Input Cloc k ( 3 Mbps) for 5-V Operation D Support s Up To 32-MHz Oscillator Input Clock ( 2 Mbps) for 3.3-V Operation D 64-Byte Transmit FIFO D 64-Byte Receive FIFO Wi th Error Flags D Pr.
Manufacture

Texas Instruments

Datasheet
Download TL16C754B Datasheet




 TL16C754B
TL16C754B
QUAD UART WITH 64ĆBYTE FIFO
D ST16C654 Pin Compatible With Additional
Enhancements
D Supports Up To 24-MHz Crystal Input Clock
( 1.5 Mbps)
D Supports Up To 48-MHz Oscillator Input
Clock ( 3 Mbps) for 5-V Operation
D Supports Up To 32-MHz Oscillator Input
Clock ( 2 Mbps) for 3.3-V Operation
D 64-Byte Transmit FIFO
D 64-Byte Receive FIFO With Error Flags
D Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation
D Programmable Receive FIFO Trigger Levels
for Software/Hardware Flow Control
D Software/Hardware Flow Control
− Programmable Xon/Xoff Characters
− Programmable Auto-RTS and Auto-CTS
D Optional Data Flow Resume by Xon Any
Character
D DMA Signalling Capability for Both
Received and Transmitted Data
D Supports 3.3-V or 5-V Supply
SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004
D Characterized for Operation From −40°C to
85°C
D Software Selectable Baud Rate Generator
D Prescalable Provides Additional Divide by 4
Function
D Fast Access 2 Clock Cycle IOR/IOW Pulse
Width
D Programmable Sleep Mode
D Programmable Serial Interface
Characteristics
− 5, 6, 7, or 8-Bit Characters
− Even, Odd, or No Parity Bit Generation
and Detection
− 1, 1.5, or 2 Stop Bit Generation
D False Start Bit Detection
D Complete Status Reporting Capabilities in
Both Normal and Sleep Mode
D Line Break Generation and Detection
D Internal Test and Loopback Capabilities
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
PN PACKAGE
(TOP VIEW)
NC
NC
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
NC
NC − No internal connection
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
TL16C754BPN
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC
NC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999 − 2004, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TL16C754B
TL16C754B
QUAD UART WITH 64ĆBYTE FIFO
SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004
FN PACKAGE
(TOP VIEW)
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
TL16C754BFN
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC − No internal connection
description
The TL16C754B is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3 Mbps. The TL16C754B offers enhanced features. It has
a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during
hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY
for all four ports in one access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows onboard diagnostics.
The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
The TL16C754B is available in 80-pin TQFP and 68-pin PLCC packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TL16C754B
TL16C754B
QUAD UART WITH 64ĆBYTE FIFO
SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004
Terminal Functions
TERMINAL
NAME
NO.
I/O
PN
FN
DESCRIPTION
A0
30
34
I Address bit 0 select. Internal registers address selection. Refer to Table 7 for Register Address Map.
A1
29
33
I Address bit 1 select. Internal registers address selection. Refer to Table 7 for Register Address Map
A2
28
32
I Address bit 2 select. Internal registers address selection. Refer to Table 7 for Register Address Map
CDA, CDB
CDC, CDD
79, 23 9, 27
39, 63 43, 61
I
Carrier detect (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates that a carrier has been detected by the modem for that channel.
CLKSEL
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects
26
30
I the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value.
CSA, CSB
CSC, CSD
9, 13, 16, 20,
49, 53 50, 54
I
Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU
and the TL16C754B for the channel(s) addressed. Individual UART sections (A, B, C, D) are
addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A through
CTSA, CTSB
CTSC, CTSD
4, 18 11, 25
44, 58 45, 59
I
D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
754A. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7,
for hardware flow control operation.
D0−D2
D3−D7
68−70, 66−68,
71−75 1−5
I/O
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
DSRA, DSRB 3, 19 10, 26
DSRC, DSRD 43, 59 44, 60
I
Data set ready (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
DTRA, DTRB
DTRC, DTRD
5, 17 12, 24
45, 57 46, 58
Data terminal ready (active low). These outputs are associated with individual UART channels A
through D. A low on these pins indicates that the 754A is powered on and ready. These pins can
O be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a
reset.
GND
16, 36,
56, 76
6, 23,
40, 57
Pwr
Signal and power ground
INTA, INTB
INTC, INTD
Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D.
8, 14, 15, 21,
48, 54 49, 55
O
INTA−D are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable
register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.
INTA−D are in the high-impedance state after reset.
INTSEL
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR
bit 3 to enable or disable the 3-state interrupts INTA-D or override MCR bit 3 and force continuous
67
65
I interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low
allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable
the 3-state outputs.
Read input (active low strobe). A valid low level on IOR will load the contents of an internal register
IOR
51
52
I defined by address bits A0−A2 onto the TL16C754B data bus (D0−D7) for access by an external
CPU.
IOW
11
18
I
Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus
(D0−D7) from the external CPU to an internal register that is defined by address bits A0−A2.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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